# TB67S580FNG

**TOSHIBA** · Motor Driver ICs · HTSSOP-28

TB67S580FNG from TOSHIBA, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Non-connection pin; do not run patterns under NC pins. |
| 2 | NC | unconnected | Non-connection pin; do not run patterns under NC pins. |
| 3 | NC | unconnected | Non-connection pin; do not run patterns under NC pins. |
| 4 | VM | power_in | Motor power supply pin (HSW_Ach); operating range 8.2 V to 44 V, absolute maximum 45 V. |
| 5 | OUTA1 | output | H-bridge Ach output + pin; motor output voltage absolute maximum 50 V. |
| 6 | RSA | passive | H-bridge Ach current sense resistor connection pin; set current IOUT = VREF / 5 / RRS. |
| 7 | OUTA2 | output | H-bridge Ach output - pin; motor output voltage absolute maximum 50 V. |
| 8 | OUTB2 | output | H-bridge Bch output - pin; motor output voltage absolute maximum 50 V. |
| 9 | RSB | passive | H-bridge Bch current sense resistor connection pin; set current IOUT = VREF / 5 / RRS. |
| 10 | OUTB1 | output | H-bridge Bch output + pin; motor output voltage absolute maximum 50 V. |
| 11 | VM | power_in | Motor power supply pin (HSW_Bch); operating range 8.2 V to 44 V, absolute maximum 45 V. |
| 12 | VREFA | input | Current set reference input pin for H-bridge Ach; VREF operating range 1 V to 3.6 V. |
| 13 | VREFB | input | Current set reference input pin for H-bridge Bch; VREF operating range 1 V to 3.6 V. |
| 14 | AGND | power_in | Analog ground pin. |
| 15 | VREG | power_out | 3.3 V regulator voltage output pin (3.2 V to 3.4 V at Iout = 1 mA). |
| 16 | RESET_X | input | Reset input pin; Low initializes the internal electrical angle, High is normal operation. |
| 17 | SLEEP_X | input | Sleep mode input pin; Low is low-power sleep mode, High is normal operation, with 4.3 ms wakeup time. |
| 18 | LO | output | Error detection flag output pin; needs an external pull-up (10 kΩ to 100 kΩ). |
| 19 | DECAY | input | Decay mode select pin; Low is slow decay, High is fast decay, Open is mixed decay. |
| 20 | CW_CCW | input | Rotation direction set pin; Low is counter-clockwise, High is clockwise. |
| 21 | ENABLE_X | input | Enable input pin; Low turns H-bridge outputs ON, High turns them OFF (Hi-Z). |
| 22 | CLK | input | Step clock input pin; each rising edge advances the step, max clock frequency 250 kHz. |
| 23 | NC | unconnected | Non-connection pin; do not run patterns under NC pins. |
| 24 | DMODE0 | input | Step mode select pin (bit 0) selecting full to 1/32 step resolution. |
| 25 | DMODE1 | input | Step mode select pin (bit 1) selecting full to 1/32 step resolution. |
| 26 | DMODE2 | input | Step mode select pin (bit 2) selecting full to 1/32 step resolution. |
| 27 | MO | output | Electrical angle monitor pin; Low at initial position, needs an external pull-up (10 kΩ to 100 kΩ). |
| 28 | PGND | power_in | Power ground pin. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | HTSSOP-28 |
| Category | Power Supply Chip |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Motor output voltage | VOUT |  |  | 50 | V | Ta = 25°C | 18 |
| Motor power supply | VM |  |  | 45 | V | Ta = 25°C | 18 |
| Motor output current | IOUT |  |  | 2.5 | A | Ta = 25°C | 18 |
| Logic input voltage | VIN |  |  | 6 | V | Ta = 25°C | 18 |
| Vref reference voltage | Vref |  |  | 6 | V | Ta = 25°C | 18 |
| Monitor voltage for electrical angle | VMO |  |  | 6 | V | Ta = 25°C | 18 |
| Power dissipation | PD |  |  | 4 | W | JEDEC 4-layer PCB, Ta = 25°C; derate 32mW/°C above 25°C | 18 |
| Operating temperature | Topr | -40 |  | 85 | °C |  | 18 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 18 |
| Junction temperature | Tj(MAX) |  |  | 150 | °C |  | 18 |
| Motor power supply | VM | 8.2 | 24 | 44 | V | Ta = -40 to 85°C | 18 |
| Motor output current | IOUT |  |  | 2 | A | Per phase | 18 |
| Logic input High level | VIN(H) | 2.2 |  | 5.25 | V | Logic input High Level | 18 |
| Logic input Low level | VIN(L) | 0 |  | 0.7 | V | Logic input Low Level | 18 |
| Clock frequency | fCLK |  |  | 250 | kHz |  | 18 |
| Vref reference voltage | VREF | 1 |  | 3.6 | V |  | 18 |
| Logic input voltage High | VIN(H) | 2.2 |  | 5.25 | V | Logic input pin | 19 |
| Logic input voltage Low | VIN(L) | 0 |  | 0.7 | V | Logic input pin | 19 |
| Logic input hysteresis voltage | VIN(HYS) | 300 | 450 | 600 | mV | Logic input pin | 19 |
| Logic input current High | IIN(H) |  |  | 100 | µA | Logic input voltage: 3.3 V | 19 |
| Logic input current Low | IIN(L) | -20 |  | 20 | µA | Logic input voltage: 0 V | 19 |
| MO output pin voltage | VOL(MO) |  | 0.2 | 0.5 | V | IOL=5 mA, Output: Low | 19 |
| Power consumption (sleep) | IM1 |  | 10 | 20 | µA | Output pin: Open, Sleep mode | 19 |
| Power consumption (operating) | IM2 |  | 5 | 8 | mA | Output pin: Open, Operating mode | 19 |
| Output leakage current High-side | IOH |  |  | 1 | µA | VM = (44)V, VOUT = 0 V | 19 |
| Output leakage current Low-side | IOL | 1 |  |  | µA | VM = VOUT = (44) V | 19 |
| Motor current channel differential | ΔIOUT1 | -5 | 0 | 5 | % | Current differential between Ch, IOUT = 1.0 A | 19 |
| Motor current setting accuracy | ΔIOUT2 | -5 | 0 | 5 | % | IOUT = 1.0 A | 19 |
| Motor output ON-resistance (High-side + Low-side) | RON(D-S) |  | 0.4 | 0.52 | Ω | Tj = 25°C, IOUT = 2.0 A | 19 |
| Vref input current | IREF | -3 |  | 3 | µA | Vref = 3.3 V | 20 |
| VREG voltage | VREG | 3.2 | 3.3 | 3.4 | V | Iout=1mA | 20 |
| TSD threshold | TjTSD | 150 | 160 | 180 | °C |  | 20 |
| Vref decay ratio | VREF(GAIN) |  | 5 |  |  | Vref = (2.0 V) | 20 |
| TSD hysteresis | TTSDHYS |  | 30 |  | °C |  | 20 |
| Over current detection circuit operating current | ISD |  | 3 |  | A |  | 20 |
| Minimum clock pulse width High | tCLK(H) | 1.9 |  |  | µs |  | 21 |
| Minimum clock pulse width Low | tCLK(L) | 1.9 |  |  | µs |  | 21 |
| Setup time | tSU(STEP) | 650 |  |  | ns |  | 21 |
| Hold time | tH(STEP) | 650 |  |  | ns |  | 21 |
| Output transistor rise time | tr |  | 30 | 200 | ns |  | 21 |
| Output transistor fall time | tf |  | 30 | 200 | ns |  | 21 |

## CAD (KiCad official)

- Symbol: `TB67S580FNG`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `tb67s580fng-etched.step` / `tb67s580fng-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tb67s580fng.step` / `tb67s580fng.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TOSHIBA datasheet](docs/tb67s580fng-datasheet.pdf) (26 pp, sha256 `c860a65400108f3a`, retrieved 2026-10-24, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tb67s580fng-datasheet.pdf)