component
TB67S249FTG
Public Made by Adomby adom
TOSHIBA Motor Driver ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 12d ago |
| viewers | 12d ago |
| package.json | 12d ago |
| page.json | 12d ago |
| README.md | 12d ago |
| tb67s249ftg-etched.glb | 12d ago |
| tb67s249ftg-etched.step | 12d ago |
| tb67s249ftg-hero.glb | 12d ago |
| tb67s249ftg-hero.overlay.json | 12d ago |
| tb67s249ftg.glb | 12d ago |
| tb67s249ftg.kicad_mod | 12d ago |
| tb67s249ftg.kicad_sym | 12d ago |
| tb67s249ftg.lbr | 12d ago |
| tb67s249ftg.step | 12d ago |
TB67S249FTG
TOSHIBA · Motor Driver ICs · QFN-48-EP(7x7)
TB67S249FTG from TOSHIBA, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGC0 | input | Active Gain Control setup pin No.0, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 2 | AGC1 | input | Active Gain Control setup pin No.1, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 3 | CLIM0 | input | AGC current limiter setup pin No.0, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 4 | CLIM1 | input | AGC current limiter setup pin No.1, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 5 | FLIM | input | AGC frequency limiter setup pin, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 6 | BOOST | input | AGC current boost setup pin, a multi-state input tied to VCC, GND, VCC via 100 kΩ pull-up, or GND via 100 kΩ pull-down. |
| 7 | LTH | input | AGC threshold setup pin with an internal 100 kΩ pull-down (±20 % accuracy). |
| 8 | GND | power_in | Ground pin; connect pins of the same name together at the nearest point of the driver. |
| 9 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 10 | VMA | power_in | Motor power supply input pin for Ach, operating range 10 V to 47 V. |
| 11 | VMA | power_in | Motor power supply input pin for Ach, operating range 10 V to 47 V. |
| 12 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 13 | OUTA+ | output | Ach motor output (+) pin, output voltage range 10 V to 47 V. |
| 14 | OUTA+ | output | Ach motor output (+) pin, output voltage range 10 V to 47 V. |
| 15 | RSAGND | power_in | Ach motor power ground pin. |
| 16 | RSAGND | power_in | Ach motor power ground pin. |
| 17 | OUTA- | output | Ach motor output (-) pin, output voltage range 10 V to 47 V. |
| 18 | OUTA- | output | Ach motor output (-) pin, output voltage range 10 V to 47 V. |
| 19 | OUTB- | output | Bch motor output (-) pin, output voltage range 10 V to 47 V. |
| 20 | OUTB- | output | Bch motor output (-) pin, output voltage range 10 V to 47 V. |
| 21 | RSBGND | power_in | Bch motor power ground pin. |
| 22 | RSBGND | power_in | Bch motor power ground pin. |
| 23 | OUTB+ | output | Bch motor output (+) pin, output voltage range 10 V to 47 V. |
| 24 | OUTB+ | output | Bch motor output (+) pin, output voltage range 10 V to 47 V. |
| 25 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 26 | VMB | power_in | Motor power supply input pin for Bch, operating range 10 V to 47 V. |
| 27 | VMB | power_in | Motor power supply input pin for Bch, operating range 10 V to 47 V. |
| 28 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 29 | GND | power_in | Ground pin; connect pins of the same name together at the nearest point of the driver. |
| 30 | GND | power_in | Ground pin; connect pins of the same name together at the nearest point of the driver. |
| 31 | VREFB | input | Bch current threshold reference pin, input voltage range GND to 3.6 V. |
| 32 | VREFA | input | Ach current threshold reference pin, input voltage range GND to 3.6 V. |
| 33 | VCC | power_out | Internal regulator voltage monitor pin, VCC range 4.75 V to 5.25 V. |
| 34 | VCC | power_out | Internal regulator voltage monitor pin, VCC range 4.75 V to 5.25 V. |
| 35 | OSCM | bidirectional | Internal oscillator frequency monitor and setting pin, frequency range 0.64 MHz to 2.4 MHz. |
| 36 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 37 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 38 | NC | unconnected | Non connection; leave open and do not connect any PCB pattern. |
| 39 | DMODE0 | input | Step resolution setting pin No.0 (logic input, low ≤ 0.8 V, high 2.0 V to 5.5 V); all three DMODE pins low selects standby mode. |
| 40 | DMODE1 | input | Step resolution setting pin No.1 (logic input, low ≤ 0.8 V, high 2.0 V to 5.5 V); all three DMODE pins low selects standby mode. |
| 41 | DMODE2 | input | Step resolution setting pin No.2 (logic input, low ≤ 0.8 V, high 2.0 V to 5.5 V); all three DMODE pins low selects standby mode. |
| 42 | CW/CCW | input | Current direction setup pin; High is clockwise (Ach current leads Bch by 90°), Low is counter-clockwise. |
| 43 | CLK | input | Step clock input pin; each rising edge shifts the electrical angle and current step, with a 200 ns (±20 %) analog filter. |
| 44 | ENABLE | input | Motor output ON/OFF pin; High turns outputs on, Low sets outputs to Hi-Z. |
| 45 | RESET | input | Electrical angle initialize pin; High initializes the internal electrical angle, Low is normal operation. |
| 46 | MO | output | Electrical angle monitor, open-drain output that goes Low at the initial electrical angle; pull up to VCC with 10 kΩ to 100 kΩ. |
| 47 | LO1 | output | Error flag output pin No.1, logic output with VOL ≤ 0.5 V and VOH 4.75 V to 5.25 V. |
| 48 | LO2 | output | Error flag output pin No.2, logic output with VOL ≤ 0.5 V and VOH 4.75 V to 5.25 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | QFN-48-EP(7x7) |
| Category | Power Management ICs |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Motor power supply | VM | 50 | V | Ta = 25°C | 19 | ||
| Motor output voltage | VOUT | 50 | V | Ta = 25°C | 19 | ||
| Motor output current | IOUT | 4.5 | A | Ta = 25°C, Note1 | 19 | ||
| Internal logic power supply | VCC | 6 | V | Ta = 25°C | 19 | ||
| Logic input voltage high | VIN (H) | 6 | V | Ta = 25°C | 19 | ||
| Logic input voltage low | VIN (L) | -0.4 | V | Ta = 25°C | 19 | ||
| MO output voltage | VMO | 6 | V | Ta = 25°C | 19 | ||
| LO output voltage | VLO | 6 | V | Ta = 25°C | 19 | ||
| MO inflow current | IMO | 6 | mA | Ta = 25°C | 19 | ||
| LO inflow current | ILO | 6 | mA | Ta = 25°C | 19 | ||
| Power dissipation | PD | 1.3 | W | Device alone (Ta = 25°C), Note2 | 19 | ||
| Operating temperature | Topr | -20 | 85 | °C | 19 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 19 | ||
| Junction temperature | Tj (max) | 150 | °C | 19 | |||
| Motor power supply | VM | 10 | 24 | 47 | V | Ta=-20 to 85°C | 19 |
| Motor output current | IOUT | 2.25 | 4.5 | A | Ta=-20 to 85°C, Note1 | 19 | |
| MO output pin voltage | VMO | 3.3 | V | Pull-up voltage, max VCC | 19 | ||
| LO output pin voltage | VLO | 3.3 | V | Pull-up voltage, max VCC | 19 | ||
| Clock input frequency | fCLK | 1000 | kHz | Ta=-20 to 85°C, Note2 | 19 | ||
| Chopping frequency (range) | Fchop | 40 | 70 | 150 | kHz | Ta=-20 to 85°C | 19 |
| VREF input voltage | VREF | 0 | 2 | 3.6 | V | Ta=-20 to 85°C, min is GND | 19 |
| Logic input voltage 1 high | VIN1 (H) | 2 | 5.5 | V | High level | 20 | |
| Logic input voltage 1 low | VIN1 (L) | 0 | 0.8 | V | Low level | 20 | |
| Logic input hysteresis voltage | VIN (HYS) | 0.1 | 0.3 | V | Hysteresis voltage | 20 | |
| Logic input voltage 2 high | VIN2 (H) | 4.2 | V | VCC short (BOOST, CLIM1, FLIM); max VCC | 20 | ||
| Logic input voltage 2 pull-up | VIN2 (PU) | 2.8 | 3.55 | V | VCC-100 kΩ pull-up | 20 | |
| Logic input voltage 2 pull-down | VIN2 (PD) | 1.45 | 2.2 | V | GND-100 kΩ pull-down | 20 | |
| Logic input voltage 2 low | VIN2 (L) | 0 | 0.8 | V | GND short | 20 | |
| Logic input current 1 high | IIN1 (H) | 33 | µA | Input voltage=3.3 V | 20 | ||
| Logic input current 1 low | IIN1 (L) | 1 | µA | Input voltage=0 V | 20 | ||
| MO output pin voltage | VOL (MO) | 0.2 | 0.5 | V | IOL=5 mA LO=Low | 20 | |
| LO output pin voltage | VOL (LO) | 0.2 | 0.5 | V | IOL=5 mA LO=Low | 20 | |
| Current consumption standby | IM1 | 2 | mA | Standby mode | 20 | ||
| Current consumption | IM2 | 3 | 5 | 7 | mA | OUT: OPEN, ENABLE: Low, Standby mode: Release | 20 |
| Current consumption | IM3 | 4 | 6 | 8 | mA | OUT: OPEN, ENABLE: High, Standby mode: Release | 20 |
| Output leakage current high-side | IOH | 1 | µA | VM=50 V,VOUT=0 V | 20 | ||
| Output leakage current low-side | IOL | 1 | µA | VM=VOUT=50 V | 20 | ||
| Motor current channel differential | ΔIOUT1 | -5 | 0 | 5 | % | Current differential between channels | 20 |
| Motor current setting differential | ΔIOUT2 | -5 | 0 | 5 | % | IOUT=1.5 A | 20 |
| Motor output ON-resistance (High-side + Low-side) | Ron (H+L) | 0.33 | 0.45 | Ω | Tj=25°C, Forward direction (High + Low side) | 20 | |
| VREF input current | IREF | 0 | 1 | μA | VREF=2.0 V | 21 | |
| VCC voltage | VCC | 4.75 | 5 | 5.25 | V | ICC=5.0 mA | 21 |
| VCC current | ICC | 2.5 | 5 | mA | VCC=5.0 V | 21 | |
| VREF gain | VREF (gain) | 1.25 | A/V | VREF=2.0 V | 21 | ||
| Thermal shutdown threshold | TjTSD | 145 | 160 | 175 | °C | Note1 | 21 |
| VM power-on-reset threshold release | VMPOR (H) | 6.5 | 7.5 | 8.5 | V | POR release | 21 |
| VM power-on-reset threshold detect | VMPOR (L) | 6 | 7 | 8 | V | POR detect | 21 |
| Over current protection threshold | ISD | 5 | 6 | 7 | A | Note 2 | 21 |
| Minimum CLK high pulse width | tCLK (H) | 500 | ns | CLK (H) minimum pulse width | 22 | ||
| Minimum CLK low pulse width | tCLK (L) | 500 | ns | CLK (L) minimum pulse width | 22 | ||
| Output MOSFET rise time | tr | 60 | 110 | 160 | ns | 22 | |
| Output MOSFET fall time | tf | 60 | 110 | 160 | ns | 22 | |
| OSCM oscillator accuracy 1 | ΔfOSCM1 | -15 | 15 | % | COSC=270 pF, ROSC=5.1 kΩ | 22 | |
| OSCM oscillator accuracy 2 | ΔfOSCM2 | -20 | 20 | % | COSC: GND short, ROSC: Open | 22 | |
| Propagation delay CLK to OUT (low-to-high) | tpLH (CLK) | 1000 | ns | CLK to OUT | 22 | ||
| Propagation delay CLK to OUT (high-to-low) | tpHL (CLK) | 1100 | ns | CLK to OUT | 22 | ||
| PWM chopping frequency 1 | fchop1 | 67 | kHz | COSC=270 pF, ROSC=5.1 kΩ | 22 | ||
| PWM chopping frequency 2 | fchop2 | 57 | kHz | COSC: GND short, ROSC: Open | 22 |
CAD (KiCad official)
- Symbol:
TB67S249FTG - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
tb67s249ftg-etched.step/tb67s249ftg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tb67s249ftg.step/tb67s249ftg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (27 pp, sha256
325b47dcac10e265, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).