component
TB67H401FTG
Public Made by Adomby adom
TOSHIBA Motor Driver ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTB67H401FTG
TOSHIBA · Motor Driver ICs · VQFN-48-EP(7x7)
TB67H401FTG from TOSHIBA, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 2 | INB1 | input | H-bridge control pin No.1 for Bch; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 3 | INB2 | input | H-bridge control pin No.2 for Bch; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 4 | TBLKAB | input | Noise filter setting pin for constant current circuit; L sets digital tBLK to 4 OSCM clocks and H sets it to 6 OSCM clocks. |
| 5 | GND | power_in | Ground pin. |
| 6 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 7 | RSA | passive | Current sense pin for Ach. |
| 8 | RSA | passive | Current sense pin for Ach. |
| 9 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 10 | OUTA+ | output | Motor output (+) pin for Ach; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 11 | OUTA+ | output | Motor output (+) pin for Ach; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 12 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 13 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 14 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 15 | GND | power_in | Power ground pin for H-bridge. |
| 16 | OUTA- | output | Motor output (-) pin for Ach; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 17 | OUTA- | output | Motor output (-) pin for Ach; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 18 | GND | power_in | Ground pin. |
| 19 | GND | power_in | Ground pin. |
| 20 | OUTB- | output | Motor output (-) pin for Bch; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 21 | OUTB- | output | Motor output (-) pin for Bch; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 22 | GND | power_in | Power ground pin for H-bridge. |
| 23 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 24 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 25 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 26 | OUTB+ | output | Motor output (+) pin for Bch; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 27 | OUTB+ | output | Motor output (+) pin for Bch; output voltage range is 10 V ≤ VM ≤ 47 V. |
| 28 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 29 | RSB | passive | Current sense pin for Bch. |
| 30 | RSB | passive | Current sense pin for Bch. |
| 31 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 32 | VM | power_in | Motor power supply pin; operating voltage range is 10 V ≤ VM ≤ 47 V. |
| 33 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 34 | VCC | power_out | Internal regulator voltage monitor pin; VCC must be within 4.75 V to 5.25 V. |
| 35 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 36 | LO | output | Error detection flag; logic output at 0 V to 0.5 V for low and 4.5 V to 5.5 V for high. |
| 37 | FBB | output | Current detection flag for Bch. |
| 38 | FBA | output | Current detection flag for Ach. |
| 39 | HBMODE | input | H-bridge drive mode setting pin; connect to VCC for single H-bridge mode or to GND for dual H-bridge mode, and do not switch during operation. |
| 40 | GND | power_in | Ground pin. |
| 41 | VREFB | input | Current threshold reference pin for Bch; VREF input voltage range is GND to 4.0 V. |
| 42 | VREFA | input | Current threshold reference pin for Ach; VREF input voltage range is GND to 4.0 V. |
| 43 | OSCM | passive | Internal oscillator frequency setting pin; oscillator frequency range is 0.64 MHz to 2.4 MHz. |
| 44 | INA1 | input | H-bridge control pin No.1 for Ach; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 45 | INA2 | input | H-bridge control pin No.2 for Ach; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 46 | PWMA | input | Short brake pin for Ach; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 47 | PWMB | input | Short brake pin for Bch; logic input 0 V to 0.8 V for low and 2.0 V to 5.5 V for high. |
| 48 | NC | unconnected | Non connection; do not connect any PCB pattern to this pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management ICs |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Motor power supply | VM | 50 | V | 15 | |||
| Motor output voltage | VOUT | 50 | V | 15 | |||
| Motor output current | IOUT(SHB) | 6 | A | Note1: HBMODE pin high | 15 | ||
| Motor output current | IOUT(DHB) | 3 | A/ch | Note2: HBMODE pin low | 15 | ||
| Internal logic power supply | VCC | 6 | V | 15 | |||
| Logic input voltage HIGH | VIN(H) | 6 | V | 15 | |||
| Logic input voltage LOW | VIN(L) | -0.4 | V | 15 | |||
| LO output voltage | VLO | 6 | V | 15 | |||
| LO inflow current | ILO | 6 | mA | 15 | |||
| Power dissipation | PD | 1.3 | W | Note3: Device alone (Ta = 25°C) | 15 | ||
| Operating temperature | Topr | -20 | 85 | °C | 15 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 15 | ||
| Junction temperature (max) | Tj (max) | 150 | °C | 15 | |||
| Motor power supply | VM | 10 | 24 | 47 | V | Ta=-20 to 85°C | 15 |
| Motor output current | IOUT(SHB) | 3 | 6 | A | Note1: HBMODE pin high | 15 | |
| Motor output current | IOUT(DHB) | 1.5 | 3 | A/ch | Note2: HBMODE pin low | 15 | |
| LO output voltage | VLO | 3.3 | V | 15 | |||
| Chopping frequency (range) | fchop | 40 | 70 | 150 | kHz | 15 | |
| VREF input voltage | VREF | 2 | 4 | V | 15 | ||
| Logic input voltage HIGH | VIN(H) | 2 | 5.5 | V | High level (Note) | 16 | |
| Logic input voltage LOW | VIN(L) | 0 | 0.8 | V | Low level (Note) | 16 | |
| Logic input hysteresis voltage | VIN(HYS) | 0.1 | 0.3 | V | Hysteresis voltage | 16 | |
| Logic input current LOW | IIN(L) | 1 | µA | Input voltage = 0 V | 16 | ||
| Logic output pin voltage HIGH (FBB,FBA,LO) | VO(H) | 4.5 | 4.8 | 5.5 | V | IOL = 5 mA LO = Low (10 kΩ,5V Pull Up) | 16 |
| Logic output pin voltage LOW (FBB,FBA,LO) | VO(L) | 0 | 0.2 | 0.5 | V | 16 | |
| Current consumption | IM2 | 3.5 | 5.5 | mA | OUT: OPEN, INA1, INA2, INB1, and INB2: Low, Standby mode: Release | 16 | |
| Current consumption | IM3 | 5.5 | 7 | mA | OUT: OPEN, Standby mode: Release | 16 | |
| Output leakage current high-side | IOH | 1 | µA | VM = 50 V, VOUT = 0 V | 16 | ||
| Output leakage current low-side | IOL | 1 | µA | VM = VOUT = 50 V | 16 | ||
| Motor current channel differential | ΔIOUT1 | -5 | 0 | 5 | % | Current differential between channels | 16 |
| Motor current setting differential | ΔIOUT2 | -5 | 0 | 5 | % | IOUT = 1.6 A, HBMODE = Low | 16 |
| Motor output ON-resistance (high-side + low-side) | Ron(H+L) | 0.49 | 0.6 | Ω | Tj = 25°C, Forward direction (High side + Low side) | 16 | |
| VREF input current | IREF | 0 | 1 | µA | VREF = 2.0 V | 17 | |
| VCC voltage | VCC | 4.75 | 5 | 5.25 | V | ICC = 5.0 mA | 17 |
| VCC current | ICC | 2.5 | 5 | mA | VCC = 5.0 V | 17 | |
| Thermal shutdown (TSD) threshold | TjTSD | 145 | 160 | 175 | °C | 17 | |
| VM power-on-reset threshold | VMPOR | 7 | 8 | 9 | V | Power-on-reset release | 17 |
| Over current detection (ISD) threshold | ISD | 4.1 | 4.9 | 5.7 | A | 17 | |
| Minimum logic High pulse width | tw(H) | 500 | ns | Logic input signal | 18 | ||
| Minimum logic Low pulse width | tw(L) | 500 | ns | Logic input signal | 18 | ||
| Output MOSFET rise time | tr | 30 | 80 | 130 | ns | 18 | |
| Output MOSFET fall time | tf | 40 | 90 | 140 | ns | 18 | |
| Propagation delay low-to-high | tpLH | 250 | 1200 | ns | INA1/INB1, INA2/INB2 and PWMA/PWMB to OUT | 18 | |
| Propagation delay high-to-low | tpHL | 250 | 1200 | ns | INA1/INB1, INA2/INB2 and PWMA/PWMB to OUT | 18 | |
| Logic output delay time (current limit NF detect, FBA/FBB On) | tp(hz) | 135 | 355 | ns | Pull up 10 kΩ to 5 V (OD ON) | 18 | |
| Logic output delay time (INA1/INB1, INA2/INB2, PWMA/PWMB to FBA/FBB Off) | tp(zh) | 135 | 535 | ns | Pull up 10 kΩ to 5 V (OD OFF) | 18 | |
| OSCM oscillator accuracy | ΔfOSCM | -15 | 15 | % | COSC = 270 pF, ROSC = 5.1 kΩ | 18 |
CAD (KiCad official)
- Symbol:
TB67H401FTG - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
tb67h401ftg-etched.step/tb67h401ftg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tb67h401ftg.step/tb67h401ftg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (25 pp, sha256
fa51eb4ef0903733, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).