component
TB67B008FTG
Public Made by Adomby adom
TOSHIBA Brushless DC (BLDC) Motor Driver, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTB67B008FTG
TOSHIBA · Brushless DC (BLDC) Motor Driver · WQFN-24(4x4)
TB67B008FTG from TOSHIBA, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COM | input | Connection pin for the center tap of the motor; absolute maximum voltage on COM is -0.3 to 25 V. |
| 2 | U | output | U-phase output pin; absolute maximum output voltage 25 V and output current 3 A. |
| 3 | RS | passive | Connection pin for the output current detecting resistor. |
| 4 | V | power_in | V-phase output pin; absolute maximum output voltage 25 V and output current 3 A. |
| 5 | W | output | W-phase output pin; absolute maximum output voltage 25 V and output current 3 A. |
| 6 | TEST | passive | Test pin; connect to ground. |
| 7 | VM | power_in | Motor power supply pin; absolute maximum power supply voltage 25 V. |
| 8 | FG_OUT | output | Rotation speed detection signal output pin (open-drain) for the TB67B008FTG (1 ppr); an external pull-up resistor is needed for High output and output current is limited to 10 mA. |
| 9 | FPWM | input | Output PWM frequency select input pin; the PWM frequency is set by the input voltage of this pin. |
| 10 | LA | input | Lead angle setting input pin; the lead angle depending on rotation speed is set by the voltage on this pin. |
| 11 | TSP | input | Speed command input pin (PWM duty cycle control) in sensorless drive mode; absolute maximum input voltage -0.3 to 6.0 V. |
| 12 | ADJ0 | input | Adjusting pin for characteristics of the speed command input; voltage range 0 V to VREG. |
| 13 | ADJ1 | input | Adjusting pin 1 for characteristics of the output PWM duty cycle (DOUT1). |
| 14 | ADJ2 | input | Adjusting pin 2 for characteristics of the output PWM duty cycle (DOUT2). |
| 15 | VREG | power_out | Reference voltage output pin; absolute maximum output current 5 mA. |
| 16 | OSCCR | passive | Internal oscillator setting pin. |
| 17 | GND | power_in | Ground connection pin. |
| 18 | VST | input | Output PWM duty cycle setting pin in DC excitation and forced commutation modes. |
| 19 | SEL_ADJ | input | Output PWM duty cycle function setting input pin. |
| 20 | FST | input | Forced commutation frequency select input pin (High about 6.4 Hz, Middle or Open about 3.2 Hz, Low about 1.6 Hz). |
| 21 | TSTEP | passive | Connection pin for a capacitor that sets the output PWM duty cycle increasing time. |
| 22 | TIP | passive | Connection pin for a capacitor that sets the DC excitation time. |
| 23 | TRE | passive | Connection pin for a capacitor that sets the restart time. |
| 24 | GND | power_in | Ground connection pin. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | WQFN-24(4x4) |
| Category | Motor Driver ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage 1 | VMopr1 | 5.5 | 12 | 22 | V | 29 | |
| Power supply voltage 2 | VMopr2 | 4 | 5 | 5.5 | V | 29 | |
| Input frequency of TSP pin | foprTSP | 0.4 | 25 | 100 | kHz | 29 | |
| Power supply voltage | VM | 25 | V | Ta = 25 °C | 28 | ||
| Input voltage (TSP pin) | VIN1 | -0.3 | 6 | V | Ta = 25 °C; TSP pin (Note1) | 28 | |
| Input voltage (COM pin) | VIN2 | -0.3 | 25 | V | Ta = 25 °C; COM pin (Note2) | 28 | |
| Input voltage (logic and analog input pins) | VIN3 | -0.3 | V | Ta = 25 °C; Note3 pins; max printed as VREG+0.3 V | 28 | ||
| Output voltage (U, V, W pins) | VOUT1 | 25 | V | Ta = 25 °C; U, V, W pins (Note4) | 28 | ||
| Output voltage (FG_OUT/LD_OUT pin) | VOUT2 | 25 | V | Ta = 25 °C; FG_OUT/LD_OUT pin (Note5) | 28 | ||
| Output current (U, V, W pins) | IOUT1 | 3 | A | Ta = 25 °C; Note9: may be limited by ambient temperature or implementation | 28 | ||
| Output current (FG_OUT/LD_OUT pin) | IOUT2 | 10 | mA | Ta = 25 °C; Note7 | 28 | ||
| Output current (VREG pin) | IOUT3 | 5 | mA | Ta = 25 °C; Note8 | 28 | ||
| Power dissipation (WQFN24) | PD1 | 3.37 | W | Ta = 25 °C; WQFN24 mounted on 4-layer FR4 74 mm x 74 mm x 1.6 mm board (Note10) | 28 | ||
| Operating temperature | Topr | -40 | 105 | °C | 28 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 28 | ||
| Maximum junction temperature | Tj | 150 | °C | Maximum junction temperature should not exceed (Note9) | 28 | ||
| Static power supply current at VM | IM | 5.5 | 8 | mA | When TSP pin = 0 V; VM = 12 V, Ta = 25 °C (table header) | 30 | |
| Dynamic power supply current at VM | IM(opr) | 6 | 8.5 | mA | When TSP pin = VREG, RS pin = TIP pin = COM pin = 0 V | 30 | |
| Input current high (FST, SEL_ADJ pins) | IIN1(H) | 100 | 150 | μA | When VIN = 5 V; FST, SEL_ADJ pins | 30 | |
| Input current low (FST, SEL_ADJ pins) | IIN1(L) | -150 | -100 | μA | When VIN = 0 V; FST, SEL_ADJ pins | 30 | |
| Input current high (TSP pin) | IIN2D(H) | 100 | 150 | μA | When VIN = VREG; TSP pin | 30 | |
| Input current low (TSP pin) | IIN2D(L) | -1 | 1 | μA | When VIN = 0 V; TSP pin | 30 | |
| Input current (ADJ0, ADJ1, ADJ2, VST, LA, FPWM pins) | IIN3 | -1 | 1 | μA | When VIN = 0 V to VREG; ADJ0, ADJ1, ADJ2, VST, LA, FPWM pins | 30 | |
| Input voltage high (TSP pin) | VIN1(H) | 2 | V | TSP pin | 30 | ||
| Input voltage low (TSP pin) | VIN1(L) | 0 | 0.8 | V | TSP pin | 30 | |
| Input voltage low (FST, SEL_ADJ pins) | VIN2(L) | 0 | V | FST, SEL_ADJ pins; max printed as VREG × 0.2 | 30 | ||
| High-level output voltage (TIP, TRE, TSTEP pins) | VH | 2.25 | 2.5 | 2.75 | V | 30 | |
| Low-level output voltage (TIP, TRE, TSTEP pins) | VL | 0.45 | 0.5 | 0.55 | V | 30 | |
| COM pin input current | ICOM | -5 | -1.3 | 1 | μA | 30 | |
| Position detection comparator offset voltage | Voffset | -10 | 0 | 10 | mV | Reference data | 30 |
| Low-level output voltage (FG_OUT/LD_OUT pins) | VLFG_OUT | 0 | 0.5 | V | When IOUT = 5 mA | 30 | |
| Leakage current (FG_OUT/LD_OUT pins) | ILFG_OUT | 0 | 2 | μA | When VOUT = 25 V | 30 | |
| ON-resistance of output transistor (U, V, W pins) high side | RON1(H) | 0.3 | 0.6 | Ω | When IOUT = -0.1 A | 30 | |
| ON-resistance of output transistor (U, V, W pins) low side | RON1(L) | 0.3 | 0.6 | Ω | When IOUT = 0.1 A | 30 | |
| ON-resistance of output transistor (U, V, W pins) high side, VM = 4.0 V | RON2(H) | 0.33 | 0.6 | Ω | When IOUT = -0.1 A, VM = 4.0 V | 30 | |
| ON-resistance of output transistor (U, V, W pins) low side, VM = 4.0 V | RON2(L) | 0.33 | 0.6 | Ω | When IOUT = 0.1 A, VM = 4.0 V | 30 | |
| Output leakage current (U, V, W pins) high | IL(H) | -10 | 0 | μA | When VOUT = 0 V | 30 | |
| Output leakage current (U, V, W pins) low | IL(L) | 0 | 10 | μA | When VOUT = 25 V | 30 | |
| Output diode forward voltage (high side) | VF(H) | 1 | 1.4 | V | When IOUT = 1.5 A; Reference data | 30 | |
| Output diode forward voltage (low side) | VF(L) | 1 | 1.4 | V | When IOUT = -1.5 A; Reference data | 30 | |
| VST ON resistance in power on | RVST | 600 | 1000 | Ω | 30 | ||
| Voltage of RS pin for current limit detection | VRS | 0.225 | 0.25 | 0.275 | V | 30 | |
| PWM oscillation frequency FPWM4 | FPWM4 | 171.5 | 190.6 | 209.7 | kHz | Reference data | 31 |
| PWM oscillation frequency FPWM3 | FPWM3 | 85.7 | 95.3 | 104.9 | kHz | Reference data | 31 |
| PWM oscillation frequency FPWM2 | FPWM2 | 42.8 | 47.7 | 52.5 | kHz | Reference data | 31 |
| PWM oscillation frequency FPWM1 | FPWM1 | 21.4 | 23.8 | 26.3 | kHz | Reference data | 31 |
| OSC frequency | OSC | 10.98 | 12.2 | 13.42 | MHz | When R = 20 kΩ and C = 180 pF; Reference data | 31 |
| Threshold current of over current detection circuit | IISD | 3 | 4.5 | 6 | A | Reference data | 31 |
| UVLO detection voltage at VM pin | VMUVLO | 3.1 | 3.4 | 3.7 | V | 31 | |
| UVLO releasing voltage at VM pin | VMUVLOR | 3.4 | 3.7 | 3.98 | V | 31 | |
| UVLO detection voltage at VREG pin | VREGUVLO | 2.7 | 3 | 3.3 | V | 31 | |
| UVLO releasing voltage at VREG pin | VREGUVLOR | 2.9 | 3.2 | 3.45 | V | 31 | |
| VREG output voltage | VREG1 | 4.5 | 5 | 5.5 | V | When IVREG = -5 mA | 31 |
| VREG output voltage at VM = 4.0 V | VREG2 | 3.6 | 3.9 | 4 | V | When IVREG = -5 mA, VM = 4.0 V | 31 |
| Thermal resistance, junction to ambient (WQFN24, 4-layer board) | θja | 37.1 | °C/W | WQFN24 mounted on 74 mm x 74 mm x 1.6 mm 4-layer FR4 board; value from PD-Ta chart annotation | 29 |
CAD (KiCad official)
- Symbol:
TB67B008FTG - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
tb67b008ftg-etched.step/tb67b008ftg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tb67b008ftg.step/tb67b008ftg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (37 pp, sha256
a710916ebfebf783, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).