# TB6569FTG

**TOSHIBA** · Motor Driver ICs · VQFN-32-EP(5x5)

TB6569FTG from TOSHIBA, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output pin 1 of the H-bridge; pins 1 and 2 are both OUT1 and must be shorted together externally. |
| 2 | OUT1 | output | Output pin 1 (duplicate pin); it must be shorted to pin 1 at the external circuit. |
| 3 | N.C. | unconnected | No-connect pin; not internally connected. |
| 4 | RSGND | power_in | Power ground pin and detection resistor pin for PWM constant-current control; pins 4 and 5 must be shorted externally. |
| 5 | RSGND | power_in | Power ground pin and detection resistor pin for PWM constant-current control (duplicate pin); it must be shorted to pin 4 externally. |
| 6 | N.C. | unconnected | No-connect pin; not internally connected. |
| 7 | OUT2 | output | Output pin 2 of the H-bridge; pins 7 and 8 are both OUT2 and must be shorted together externally. |
| 8 | OUT2 | output | Output pin 2 (duplicate pin); it must be shorted to pin 7 at the external circuit. |
| 9 | N.C. | unconnected | No-connect pin; not internally connected. |
| 10 | N.C. | unconnected | No-connect pin; not internally connected. |
| 11 | VM | power_in | Power supply voltage pin; pins 11 and 12 are both VM and must be shorted together externally. |
| 12 | VM | power_in | Power supply voltage pin (duplicate pin); it must be shorted to pin 11 at the external circuit. |
| 13 | N.C. | unconnected | No-connect pin; not internally connected. |
| 14 | N.C. | unconnected | No-connect pin; not internally connected. |
| 15 | VISD | passive | Resistor pin for overcurrent detection threshold control. |
| 16 | N.C. | unconnected | No-connect pin; not internally connected. |
| 17 | TISD | passive | Resistor pin for overcurrent detection time control. |
| 18 | PWM | input | PWM input pin for direct PWM control of motor speed. |
| 19 | VREF | power_in | Supply voltage pin for PWM constant-current control. |
| 20 | N.C. | unconnected | No-connect pin; not internally connected. |
| 21 | N.C. | unconnected | No-connect pin; not internally connected. |
| 22 | ALERT | output | Error detection output pin, an open-drain output that is high during abnormal operation (UVLO, TSD, VSD and/or ISD active). |
| 23 | OSC | passive | Capacitor pin for controlling oscillation frequency for the PWM constant-current control. |
| 24 | IN1 | input | Control signal input pin 1, used together with IN2 to select CW, CCW, Short Brake or Stop mode. |
| 25 | N.C. | unconnected | No-connect pin; not internally connected. |
| 26 | SGND | power_in | Small signal ground pin; pins 26 and 27 are both SGND and must be shorted together externally. |
| 27 | SGND | power_in | Small signal ground pin (duplicate pin); it must be shorted to pin 26 at the external circuit. |
| 28 | N.C. | unconnected | No-connect pin; not internally connected. |
| 29 | N.C. | unconnected | No-connect pin; not internally connected. |
| 30 | N.C. | unconnected | No-connect pin; not internally connected. |
| 31 | IN2 | input | Control signal input pin 2, used together with IN1 to select CW, CCW, Short Brake or Stop mode. |
| 32 | N.C. | unconnected | No-connect pin; not internally connected. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management ICs |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VM |  |  | 50 | V |  | 6 |
| Output voltage | VO |  |  | 50 | V | OUT1, OUT2 | 6 |
| Output current 1 | IO peak1 |  |  | 4.5 | A | when VM ≤ 36 V | 6 |
| Output current 2 | IO peak2 |  |  | 4 | A | when VM > 36 V | 6 |
| Input voltage | VIN | -0.3 |  | 5.5 | V |  | 6 |
| ALERT pin output voltage | VALERT |  |  | 5.5 | V |  | 6 |
| ALERT pin output current | IALERT |  |  | 5 | mA |  | 6 |
| Power dissipation (TB6569FTG) | PD2 |  |  | 3 | W | On PCB, four-layer JEDEC board | 6 |
| Operating temperature | Topr | -40 |  | 85 | °C |  | 6 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 6 |
| Supply voltage | VMopr | 10 |  | 45 | V |  | 6 |
| OSC frequency | fOSC |  |  | 500 | kHz |  | 6 |
| VREF pin input voltage | VREFopr | 0 |  | 3.6 | V |  | 6 |
| PWM frequency | fPWM |  |  | 100 | kHz |  | 6 |
| Output current (average) | IO (Ave.) |  |  | 1.5 | A | given as a guide; see Note 6 (depends on ambient temperature and mounting; junction temperature 150°C must not be exceeded) | 6 |
| Stop mode supply current | ICC1 |  | 3 | 8 | mA | Stop mode | 7 |
| CW/CCW mode supply current | ICC2 |  | 3 | 8 | mA | CW/CCW mode | 7 |
| Short Brake mode supply current | ICC3 |  | 3 | 8 | mA | Short Brake mode | 7 |
| Control input voltage, high level | VINH | 2 |  | 5.5 | V | IN1 pin, IN2 pin, PWM pin | 7 |
| Control input voltage, low level | VINL | 0 |  | 0.8 | V | IN1 pin, IN2 pin, PWM pin | 7 |
| Control input current, high level | IINH |  | 50 | 75 | μA | VIN = 5 V | 7 |
| Control input current, low level | IINL |  |  | 5 | μA | VIN = 0 V | 7 |
| VREF pin input current | IINVREF | -3 |  | 3 | μA |  | 7 |
| PWM minimum pulse width | fPWM (TW) | 1 |  |  | μs | given as a guide only | 7 |
| Output ON resistance | RON (U + L) |  | 0.55 | 0.9 | Ω | IO = 3 A | 7 |
| Output leakage current, upper | IL (U) | -2 |  |  | μA | VM = 50 V, VOUT = 0 V | 7 |
| Output leakage current, lower | IL (L) |  |  | 2 | μA | VM = VOUT = 50 V | 7 |
| Diode forward voltage, upper | VF (U) |  | 1.3 | 1.7 | V | IO = 3 A | 7 |
| Diode forward voltage, lower | VF (L) |  | 1.3 | 1.7 | V | IO = −3 A | 7 |
| ALERT output low voltage | VAL (LO) |  |  | 0.4 | V | IALERT = 1 mA | 7 |
| ALERT output leakage current | IAL (LE) |  |  | 2 | μA | VALERT = 5.5 V | 7 |
| OSC charge/discharge current | IOSC | 0.3 | 0.5 | 0.7 | mA |  | 7 |
| Thermal resistance, junction-to-ambient (TB6569FTG) | Rth (j-a) |  | 41.3 |  | °C/W | On PCB, four-layer JEDEC board; PD = 3 W at Ta = 25°C | 8 |

## CAD (KiCad official)

- Symbol: `TB6569FTG`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tb6569ftg-etched.step` / `tb6569ftg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tb6569ftg.step` / `tb6569ftg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TOSHIBA datasheet](docs/tb6569ftg-datasheet.pdf) (23 pp, sha256 `4020fa861af8ed55`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tb6569ftg-datasheet.pdf)