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TAS5827RHBR

Texas Instruments · Audio Amplifiers · VQFN-32-EP(5x5)

TAS5827RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST_A+ passive Bootstrap capacitor connection for OUT_A+, creating the supply for its high-side gate drive.
2 OUT_A+ output Positive pin of differential speaker amplifier output A.
3 PVDD power_in PVDD voltage input (4.5V to 26.4V recommended).
4 PVDD power_in PVDD voltage input (4.5V to 26.4V recommended).
5 DGND power_in Digital ground.
6 DVDD power_in 3.3V or 1.8V digital supply.
7 VR_DIG power_out Internally regulated 1.5V digital supply voltage for a bypass capacitor; must not be used to drive external devices.
8 ADR input Resistor value to GND (pull-down) sets the device I2C address.
9 GPIO0 bidirectional General-purpose I/O programmable via registers 0x60 and 0x61; configurable as open-drain or push-pull output.
10 GPIO1 bidirectional General-purpose I/O programmable via registers 0x60 and 0x62; configurable as open-drain or push-pull output.
11 GPIO2 bidirectional General-purpose I/O programmable via registers 0x60 and 0x63; configurable as open-drain or push-pull output.
12 LRCLK input Word select clock for the serial port input data line; left/right boundary in I2S, LJ and RJ, frame sync in TDM.
13 SCLK input Bit clock for the serial data port input data line.
14 SDIN input Serial data port data line.
15 SDA bidirectional I2C serial control data interface input/output.
16 SCL input I2C serial control clock input.
17 PDN input Active-low power down; puts the amplifier in shutdown and turns off all internal regulators.
18 GVDD power_out Gate drive internal regulator output for a bypass capacitor; must not be used to drive external devices.
19 AVDD power_out Internally regulated 5V analog supply voltage; must not be used to drive external devices.
20 AGND power_in Analog ground.
21 PVDD power_in PVDD voltage input (4.5V to 26.4V recommended).
22 PVDD power_in PVDD voltage input (4.5V to 26.4V recommended).
23 OUT_B+ output Positive pin of differential speaker amplifier output B.
24 BST_B+ passive Bootstrap capacitor connection for OUT_B+, creating the supply for its high-side gate drive.
25 PGND power_in Ground reference for power device circuitry; connect to system ground.
26 PGND power_in Ground reference for power device circuitry; connect to system ground.
27 OUT_B- output Negative pin of differential speaker amplifier output B.
28 BST_B- passive Bootstrap capacitor connection for OUT_B-, creating the supply for its high-side gate drive.
29 BST_A- passive Bootstrap capacitor connection for OUT_A-, creating the supply for its high-side gate drive.
30 OUT_A- output Negative pin of differential speaker amplifier output A.
31 PGND power_in Ground reference for power device circuitry; connect to system ground.
32 PGND power_in Ground reference for power device circuitry; connect to system ground.
33 PowerPAD power_in Ground; connect to a ground heat sink for best system performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Amplifiers/Comparators
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DVDD-referenced digital input high current /IIH/ 10 uA VIN(DigIn) = VDVDD 10
DVDD-referenced digital input low current /IIL/ -10 uA VIN(DigIn) = 0V 10
Digital input logic high threshold VIH(Digin) 70 % VDVDD 10
Digital input logic low threshold VIL(Digin) 30 % VDVDD 10
Output logic high voltage level VOH(Digin) 80 % VDVDD IOH = 4mA 10
Output logic low voltage level VOL(Digin) 20 % VDVDD IOH = -4mA 10
Allowed load capacitance per I2C line CL(I2C) 400 pF 10
Supported SCL frequency (fast and fast+ modes) fSCL(fast) 400 1000 kHz 无等待状态,支持快速和快速+ 模式 10
Supported SCL frequency (slow mode) fSCL(slow) 100 kHz 无等待状态,慢速模式 10
SCLK duty cycle allowed DSCLK 40 60 % 10
Supported input sample rate fS 32 192 kHz 10
Supported SCLK frequency fSCLK 32 64 fS 10
Speaker amplifier programmable gain AV(SPK_AMP) 13.75 29.4 dBV 在 0dB 输入 (1FS) 时测得;值表示“峰值电压”,忽略因 PVDD 较低而导致的削波 10
Speaker output overcurrent error threshold (speaker current) OCETHRES 7.5 8 8.5 A 扬声器输出电流(后置 LC 滤波器),LC 滤波器 = 10uH + 0.68uF,BTL 模式 11
PVDD undervoltage error threshold UVETHRES(PVDD) 3.7 4 4.2 V 11
PVDD overvoltage error threshold OVETHRES(PVDD) 27 28.1 29.2 V 11
Amplifier offset voltage (stereo BTL) /VOS/ -5 5 mV 使用零输入数据以差动方式进行测量,使用 29.4dBV 模拟增益配置的可编程增益,VPVDD 范围:12V~24V 12
Amplifier offset voltage (mono PBTL) /VOS/ -5 5 mV 使用零输入数据以差动方式进行测量,使用 29.4dBV 模拟增益配置的可编程增益,VPVDD = 12V-25V 范围,1SPW 模式 13
Bus capacitive load per bus (I2C Fast mode) Cb 400 pF 14
Bus capacitive load per bus (I2C Fast+ mode) Cb 550 pF 14
Data hold time (I2C Fast mode) tD-HD 0 900 ns 14

CAD (KiCad official)

  • Symbol: TAS5827RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tas5827rhbr-etched.step / tas5827rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tas5827rhbr.step / tas5827rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 5024fb3fdb422cdc, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF