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TAS5731MPHPR

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Texas Instruments Audio Amplifiers, TQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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TAS5731MPHPR

Texas Instruments · Audio Amplifiers · TQFP-48-EP(7x7)

TAS5731MPHPR from Texas Instruments, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT_A output Half-bridge A PWM audio output pin.
2 PVDD_AB power_in Power-supply input for half-bridges A and B (8 to 26.4 V); requires 100-nF ceramic decoupling capacitor placed close to pin.
3 PVDD_AB power_in Power-supply input for half-bridges A and B (8 to 26.4 V); requires 100-nF ceramic decoupling capacitor placed close to pin.
4 BST_A power_in High-side bootstrap supply for half-bridge A gate driver; connect 10-nF ceramic capacitor to OUT_A.
5 NC unconnected No internal connection; may be left floating or connected to ground.
6 SSTIMER passive Soft-start ramp time control; leave floating for BD mode or connect 2.2-nF capacitor to ground for AD mode.
7 NC unconnected No internal connection; may be left floating or connected to ground.
8 PBTL input Mode select input with internal pulldown; logic low selects BTL mode (default), logic high selects PBTL mode.
9 AVSS power_in Analog 3.3-V supply ground connection.
10 PLL_FLTM output PLL negative loop-filter terminal; connect to external RC network with 47-nF and 4.7-nF capacitors and 470-Ω resistor.
11 PLL_FLTP output PLL positive loop-filter terminal; connect to external RC network as specified for PLL_FLTM.
12 VR_ANA power_out Internally regulated 1.8-V analog supply; must not be used to power external devices.
13 AVDD power_in 3.3-V analog power supply (3.0 to 3.6 V nominal); requires quality decoupling capacitors placed close to pin.
14 ADR/FAULT bidirectional Dual-function pin: sets I2C address to 0x36 if pulled high, 0x34 if pulled low; can be configured as active-low fault output.
15 MCLK input Master clock input (2.8224 to 24.576-MHz) with 5-V tolerance, 40-60% duty cycle, and 5-ns maximum rise/fall time.
16 OSC_RES output Oscillator trim resistor connection; connect 18.2-kΩ 1% resistor to DVSSO for oscillator frequency calibration.
17 DVSSO power_in Oscillator ground; oscillator trim resistor connects from OSC_RES to this pin.
18 VR_DIG power_out Internally regulated 1.8-V digital supply; must not be used to power external devices.
19 PDN input Active-low power-down input with internal pullup; initiates PWM stop sequence and noise shaper shutdown.
20 LRCLK input I2S left/right clock (sample-rate clock) input with 5-V tolerance; supports 8 to 48-kHz sample rates.
21 SCLK input I2S serial bit clock input (1.024 to 12.288-MHz at 32×, 48×, or 64×fS) with 5-V tolerance and 8-ns rise/fall time.
22 SDIN input Serial audio data input supporting 16-bit, 20-bit, and 24-bit I2S, left-justified, and right-justified data formats.
23 SDA bidirectional I2C open-drain serial data line with internal pullup; requires external 4.7-kΩ pullup resistor to DVDD.
24 SCL input I2C serial control clock input supporting 100-kHz and 400-kHz operation with 5-V tolerance.
25 RESET input Active-low asynchronous reset input with internal pullup; must be held low for 100-µs minimum at power-up.
26 STEST input Factory test pin; must be connected directly to DVSS for proper operation.
27 DVDD power_in 3.3-V digital power supply (3.0 to 3.6 V nominal); requires quality decoupling capacitors placed close to pin.
28 DVSS power_in Digital ground connection.
29 GND power_in Analog ground for power stage; should be connected to system ground.
30 AGND power_in Local analog ground for power-stage output section; provides ground reference for output pins.
31 VREG power_out Digital regulator output; not to be used for powering external circuitry.
32 GVDD_OUT power_out Gate-drive regulator output derived from PVDD; supplies bootstrap charging diode for high-side gate drivers.
33 BST_D power_in High-side bootstrap supply for half-bridge D gate driver; connect 10-nF ceramic capacitor to OUT_D.
34 PVDD_CD power_in Power-supply input for half-bridges C and D (8 to 26.4 V); requires 100-nF ceramic decoupling capacitor placed close to pin.
35 PVDD_CD power_in Power-supply input for half-bridges C and D (8 to 26.4 V); requires 100-nF ceramic decoupling capacitor placed close to pin.
36 OUT_D output Half-bridge D PWM output pin for audio power amplification.
37 PGND_CD power_in Power-stage ground for half-bridges C and D.
38 PGND_CD power_in Power-stage ground for half-bridges C and D.
39 OUT_C output Half-bridge C PWM output pin for audio power amplification.
40 NC unconnected No internal connection; may be left floating or connected to ground.
41 NC unconnected No internal connection; may be left floating or connected to ground.
42 BST_C power_in High-side bootstrap supply for half-bridge C gate driver; connect 10-nF ceramic capacitor to OUT_C.
43 BST_B power_in High-side bootstrap supply for half-bridge B gate driver; connect 10-nF ceramic capacitor to OUT_B.
44 NC unconnected No internal connection; may be left floating or connected to ground.
45 NC unconnected No internal connection; may be left floating or connected to ground.
46 OUT_B output Half-bridge B PWM output pin for audio power amplification.
47 PGND_AB power_in Power-stage ground for half-bridges A and B.
48 PGND_AB power_in Power-stage ground for half-bridges A and B.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48-EP(7x7)
Category Amplifiers/Comparators
Pins 49

CAD (KiCad official)

  • Symbol: TAS5731MPHPR
  • Footprint: Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: tas5731mphpr-etched.step / tas5731mphpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tas5731mphpr.step / tas5731mphpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (71 pp, sha256 b548f5b31dc8dd9b, retrieved 2026-09-26, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF