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TAS2505TRGERQ1

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Texas Instruments Audio Power OpAmps, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TAS2505TRGERQ1

Texas Instruments · Audio Power OpAmps · VQFN-24(4x4)

TAS2505TRGERQ1 from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SPI_SEL input Selects between SPI and I2C digital interface modes (1 = SPI mode, 0 = I2C mode).
2 RST input Reset for logic, state machines, and digital filters; asserted LOW.
3 AINL input Analog single-ended line left input.
4 AINR input Analog single-ended line right input.
5 NC unconnected No connect; leave unconnected.
6 AVSS power_in Analog ground, 0 V.
7 AVDD power_in Analog core supply voltage, 1.5 V to 1.95 V, tied internally to the LDO output.
8 LDO_SEL input Select pin for the LDO; ties to either SPKVDD or SPKVSS.
9 SPKM output Class-D speaker driver inverting output.
10 SPKVDD power_in Class-D speaker driver power supply, 2.7 V to 5.5 V.
11 SPKVSS power_in Class-D speaker driver power supply ground.
12 SPKP output Class-D speaker driver noninverting output.
13 DIN input Audio serial data bus input data.
14 WCLK bidirectional Audio serial data bus word clock (input or output).
15 BCLK bidirectional Audio serial data bus bit clock (input or output).
16 MCLK input Master clock input / reference clock for the clock multiplier PLL (on startup PLLCLK = CLKIN).
17 MISO output SPI serial data output.
18 GPIO/DOUT bidirectional General-purpose I/O or audio serial bus output; can be high impedance.
19 SCL/SSZ input I2C serial clock input or SPI chip select, depending on the SPI_SEL state.
20 SDA/MOSI input I2C serial data or SPI serial data input, depending on the SPI_SEL state.
21 SCLK input Serial clock for the SPI interface.
22 IOVDD power_in I/O power supply, 1.1 V to 3.6 V.
23 DVDD power_in Digital power supply, 1.65 V to 1.95 V.
24 DVSS power_in Digital ground, 0 V.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Operational Amplifier/Comparator
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS AVDD -0.3 2.2 V 5
DVDD to DVSS DVDD -0.3 2.2 V 5
SPKVDD to SPKVSS SPKVDD -0.3 6 V 5
IOVDD to IOVSS IOVDD -0.3 3.9 V 5
Operating temperature -40 105 °C 5
Junction temperature TJ 125 °C Max 5
Storage temperature Tstg -55 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human-body model, per AEC Q100-002 5
ESD CDM V(ESD) -1500 1500 V Charged-device model, per AEC Q100-011 5
AVDD supply voltage AVDD 1.5 1.8 1.95 V Referenced to AVSS 5
DVDD supply voltage DVDD 1.65 1.8 1.95 V Referenced to DVSS 5
SPKVDD supply voltage SPKVDD 2.7 5.5 V Referenced to SPKVSS 5
IOVDD supply voltage IOVDD 1.1 1.8 3.6 V Referenced to IOVSS 5
Speaker impedance 4 Ω Load applied across class-D output pins (BTL) 5
Master clock frequency MCLK 50 MHz IOVDD = DVDD = 1.8 V 5
SCL clock frequency SCL 400 kHz 5
Operating free-air temperature TA -40 105 °C 5
Junction-to-ambient thermal resistance θJA 32.2 °C/W RGE (QFN) 24 pins 5
Junction-to-case (top) thermal resistance θJCtop 30 °C/W RGE (QFN) 24 pins 6
Junction-to-board thermal resistance θJB 9.2 °C/W RGE (QFN) 24 pins 6
Junction-to-top characterization parameter ψJT 0.3 °C/W RGE (QFN) 24 pins 6
Junction-to-board characterization parameter ψJB 9.2 °C/W RGE (QFN) 24 pins 6
Junction-to-case (bottom) thermal resistance θJCbot 2.2 °C/W RGE (QFN) 24 pins 6
Gain error -0.7 0.7 dB -1 dBFS (446 mVrms), 1-kHz input signal 7
Output low voltage VOL 0.25 V IOL = 2 TTL loads 7
Oscillator frequency 8.48 MHz Internal oscillator RC_CLK 6
Idle channel noise (4 Ω) ICN 37 μVms BTL measurement, class-D gain = 6 dB, A-weighted 6
Output voltage (4 Ω) 1.4 Vrms BTL measurement, class-D gain = 6 dB, -3-dBFS input 6
THD+N (4 Ω) THD+N -73.9 dB BTL measurement, DAC input = -6 dBFS, class-D gain = 6 dB 6
Power-supply rejection ratio PSRR 55 dB BTL measurement, ripple on SPKVDD = 200 mVPP at 1 kHz 6
Mute attenuation 103 dB Mute 6
Maximum output power (4 Ω) PO 1.1 W SPKVDD = 3.6 V, BTL, CM = 0.9V, class-D gain = 18 dB, THD = 10% 6
Maximum output power (4 Ω) PO 1.4 W SPKVDD = 4.2 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 6
Maximum output power (4 Ω) PO 0.8 W SPKVDD = 3.6 V, BTL, CM = 0.9V, class-D gain = 18 dB, THD = 1% 6
Maximum output power (4 Ω) PO 2 W SPKVDD = 5.5 V, BTL, CM = 0.9V, class-D gain = 18 dB 6
Idle channel noise (8 Ω) ICN 35.2 μVms BTL measurement, class-D gain = 6 dB, A-weighted 6
Output voltage (8 Ω) 1.4 Vrms BTL measurement, class-D gain = 6 dB, -3-dBFS input 6
THD+N (8 Ω) THD+N -73.6 dB BTL measurement, DAC input = -6 dBFS, class-D gain = 6 dB 6
Maximum output power (8 Ω) PO 0.7 W SPKVDD = 3.6 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 7
Maximum output power (8 Ω) PO 1 W SPKVDD = 4.2 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 7
Maximum output power (8 Ω) PO 1.7 W SPKVDD = 5.5 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 7
Maximum output power (8 Ω) PO 0.5 W SPKVDD = 3.6 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 7
Maximum output power (8 Ω) PO 0.8 W SPKVDD = 4.2 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 7
Maximum output power (8 Ω) PO 1.3 W SPKVDD = 5.5 V, BTL, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 7
Voltage gain (analog bypass) 4 V/V Input common-mode = 0.9 V 7
Idle channel noise (analog bypass) ICN 32.6 μVms Idle channel, IN1L and IN1R ac-shorted to ground, A-weighted 7
THD+N (analog bypass) THD+N -73.7 dB -1 dBFS (446 mVrms), 1-kHz input signal 7
Shutdown current AVDD I(AVDD) 1.32 µA Power down POR, /RST held low, SPKVDD = 4.2 V 7
Shutdown current DVDD I(DVDD) 0.04 µA Power down POR, /RST held low, SPKVDD = 4.2 V 7
Shutdown current IOVDD I(IOVDD) 0.68 µA Power down POR, /RST held low, SPKVDD = 4.2 V 7
Shutdown current SPKVDD I(SPKVDD) 2.24 µA Power down POR, /RST held low, SPKVDD = 4.2 V 7
Capacitive load 10 pF 7

CAD (KiCad official)

  • Symbol: TAS2505TRGERQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: tas2505trgerq1-etched.step / tas2505trgerq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tas2505trgerq1.step / tas2505trgerq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 12ab589a7ef42439, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF