component

TAA3040IRTWR

Public Made by Adom

by adom

Texas Instruments , WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentictaa3040irtwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
taa3040irtwr / README.md
History Download
Ray Publish 0.1.0 c1a27d7 4h ago

TAA3040IRTWR

Texas Instruments · IC · WQFN-24(4x4)

TAA3040IRTWR from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog power supply, 1.8V or 3.3V nominal.
2 AREG power_out Analog on-chip regulator output (1.8V nominal) for the analog supply, or external 1.8V analog power input.
3 VREF power_in Analog reference voltage filter output; requires a minimum 1-µF capacitor to AVSS.
4 AVSS power_in Analog ground; short directly to the board ground plane.
5 MICBIAS power_out Microphone bias output.
6 IN1P_GPI1 input Analog input 1P or general-purpose digital input 1 (digital microphone data, PLL input clock source, etc.).
7 IN1M_GPO1 bidirectional Analog input 1M or general-purpose digital output 1 (digital microphone clock, interrupt, etc.).
8 IN2P_GPI2 input Analog input 2P or general-purpose digital input 2 (digital microphone data, PLL input clock source, etc.).
9 IN2M_GPO2 bidirectional Analog input 2M or general-purpose digital output 2 (digital microphone clock, interrupt, etc.).
10 IN3P_GPI3 input Analog input 3P or general-purpose digital input 3 (digital microphone data, PLL input clock source, etc.).
11 IN3M_GPO3 bidirectional Analog input 3M or general-purpose digital output 3 (digital microphone clock, interrupt, etc.).
12 IN4P_GPI4 input Analog input 4P or general-purpose digital input 4 (digital microphone data, PLL input clock source, etc.).
13 IN4M_GPO4 bidirectional Analog input 4M or general-purpose digital output 4 (digital microphone clock, interrupt, etc.).
14 SHDNZ input Device hardware shutdown and reset, active low.
15 ADDR1_MISO bidirectional I2C target address A1 pin in I2C operation; SPI target output pin in SPI operation.
16 ADDR0_SCLK input I2C target address A0 pin in I2C operation; SPI serial bit clock in SPI operation.
17 SCL_MOSI input I2C control bus clock pin in I2C operation; SPI target input pin in SPI operation.
18 SDA_SSZ bidirectional I2C control bus data pin in I2C operation; SPI target-select pin in SPI operation.
19 IOVDD power_in Digital I/O power supply, 1.8V or 3.3V nominal.
20 GPIO1 bidirectional General-purpose digital input/output 1 (digital microphone clock or data, PLL input clock source, interrupt, etc.).
21 SDOUT output Audio serial data interface bus output.
22 BCLK bidirectional Audio serial data interface bus bit clock.
23 FSYNC bidirectional Audio serial data interface bus frame synchronization signal.
24 DREG power_out Digital regulator output for the digital core supply, 1.5V nominal.
25 Thermal Pad (VSS) power_in Thermal pad shorted to internal device ground; short directly to the board ground plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24(4x4)
Category
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD supply voltage (3.3-V operation) AVDD 3 3.3 3.6 V AVDD to AVSS, AREG generated by on-chip regulator 5
AVDD and AREG supply voltage (1.8-V operation) AVDD, AREG 1.7 1.8 1.9 V AREG internal regulator shutdown 5
IOVDD supply voltage (3.3-V operation) IOVDD 3 3.3 3.6 V IOVDD 3.3-V operation 5
IOVDD supply voltage (1.8-V operation) IOVDD 1.65 1.8 1.95 V IOVDD 1.8-V operation 5
Operating ambient temperature TA -40 105 °C 5
MCLK input clock frequency 36.864 MHz GPIOx or GPIx used as MCLK input 5
I2C bus capacitance (standard/fast mode) Cb 400 pF SCL and SDA, standard-mode and fast-mode 5
I2C bus capacitance (fast-mode plus) Cb 550 pF SCL and SDA, fast-mode plus 5
Digital output load capacitance CL 20 50 pF 5
AVDD to AVSS AVDD -0.3 3.9 V 5
AREG to AVSS AREG -0.3 2 V 5
IOVDD to VSS IOVDD -0.3 3.9 V 5
Ground voltage difference AVSS to VSS -0.3 0.3 V 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -500 500 V CDM per JESD22-C101 5
Junction-to-ambient thermal resistance RθJA 32.6 °C/W RTW (WQFN) 24 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 25 °C/W 6
Junction-to-board thermal resistance RθJB 11.9 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.9 °C/W 6
Signal-to-noise ratio, A-weighted (AVDD 3.3 V) SNR 100 104 dB IN1 differential, AC signal shorted to ground, 10-kΩ input impedance, 0-dB channel gain 6
Total harmonic distortion plus noise (AVDD 3.3 V) THD+N -95 -80 dB IN1 differential, -1-dB full-scale AC input, 10-kΩ input impedance, 0-dB channel gain 6
MICBIAS load regulation 0 0.6 1.8 % MICBIAS programmed to VREF or VREF × 1.096, measured up to max load 7
MICBIAS current drive (≥2.5 V) 20 mA MICBIAS voltage ≥ 2.5 V 7
MICBIAS current drive (<2.5 V) 10 mA MICBIAS voltage < 2.5 V 7
Low-level input voltage SHDNZ VIL(SHDNZ) -0.3 0.25 V SHDNZ pin, max is 0.25 × IOVDD 7
High-level input voltage SHDNZ VIH(SHDNZ) 0.75 0.3 V SHDNZ pin, min is 0.75 × IOVDD, max is IOVDD + 0.3 7
Low-level input voltage, 3.3-V IOVDD VIL -0.3 0.8 V All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation 7
High-level input voltage, 3.3-V IOVDD VIH 2 V All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation; max IOVDD + 0.3 7
Low-level output voltage, 3.3-V IOVDD VOL 0.4 V All digital pins except INxM_GPOx, SDA and SCL, IOL = -2 mA, IOVDD 3.3-V operation 8
Low-level output voltage, 1.8-V IOVDD VOL 0.45 V All digital pins except INxM_GPOx, SDA and SCL, IOL = -2 mA, IOVDD 1.8-V operation 8
High-level output voltage, 3.3-V IOVDD VOH 2.4 V All digital pins except INxM_GPOx, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 8
Input logic-high leakage IIH -5 0.1 5 µA All digital pins except INxP_GPIx pins, input = IOVDD 8
Input logic-low leakage IIL -5 0.1 5 µA All digital pins except INxP_GPIx pins, input = 0 V 8
I2C low-level output voltage (IOVDD > 2 V) VOL1(I2C) 0.4 V SDA, IOL(I2C) = -3 mA, IOVDD > 2 V 8
Hardware shutdown current AVDD 3.3 V IAVDD 0.5 µA SHDNZ = 0, AVDD = 3.3 V, internal AREG 8
Sleep mode current AVDD 3.3 V IAVDD 5 µA All external clocks stopped, AVDD = 3.3 V, internal AREG 8
4-channel 48-kHz AVDD current, 3.3 V IAVDD 21.3 mA ADC 4-channel at fS 48 kHz, PLL on, BCLK = 256 × fS, AVDD = 3.3 V, internal AREG 9
4-channel 48-kHz AVDD current, 1.8 V IAVDD 20.2 mA ADC 4-channel at fS 48 kHz, PLL on, BCLK = 256 × fS, AVDD = 1.8 V, external AREG 9

CAD (KiCad official)

  • Symbol: TAA3040IRTWR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: taa3040irtwr-etched.step / taa3040irtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); taa3040irtwr.step / taa3040irtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (130 pp, sha256 e8892e7ba319b56b, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF