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Ray Publish 0.1.0 aaaed17 14d ago

SZMMBZ5V6ALT1G

onsemi · ESD And Surge Protection (TVS/ESD) · SOT-23

SZMMBZ5V6ALT1G from onsemi, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CATHODE 1 passive Cathode of the first Zener junction; with pin 3 (ANODE) it forms one unidirectional clamp, or with pins 2 and 3 it forms a single bidirectional configuration.
2 CATHODE 2 passive Cathode of the second Zener junction, sharing the common anode at pin 3 to protect a second separate line in the same package.
3 ANODE passive Common anode of both Zener junctions, connected to both cathodes (pins 1 and 2) in the dual common-anode design.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOT-23
Category Circuit Protection
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Breakdown Voltage VBR 5.32 5.6 5.88 V IT = 20 mA (Note 4) 3
Maximum Reverse Leakage Current IR 5 A @ VRWM = 3.0 V 3
Clamping Voltage VC 8 V @ IPP = 3.0 A (Note 6) 3
Maximum Reverse Peak Pulse Current IPP 3 A Surge waveform per Figure 6 (Note 6) 3
Maximum Zener Impedance ZZT 11 Ω @ IZT = 20 mA; IZ(AC) = 0.1 IZ(DC), 1.0 kHz (Note 5) 3
Maximum Zener Impedance ZZK 1600 Ω @ IZK = 0.25 mA (Note 5) 3
Forward Voltage VF 0.9 V @ IF = 10 mA 3
Maximum Temperature Coefficient of VBR VBR 1.26 mV/C 3
Working Peak Reverse Voltage VRWM 3 V 3
Peak Power Dissipation Ppk 24 W @ 1.0 ms (Note 1), TL ≤ 25°C 2
Total Power Dissipation on FR-5 Board PD 225 mW @ TA = 25°C (Note 2) 2
Derate above 25°C, FR-5 Board 1.8 mW/°C Derate above 25°C (Note 2) 2
Thermal Resistance Junction-to-Ambient, FR-5 Board RθJA 556 °C/W FR-5 board (Note 2) 2
Total Power Dissipation on Alumina Substrate PD 300 mW @ TA = 25°C (Note 3) 2
Derate above 25°C, Alumina Substrate 2.4 mW/°C Derate above 25°C (Note 3) 2
Thermal Resistance Junction-to-Ambient, Alumina Substrate RθJA 417 °C/W Alumina substrate (Note 3) 2
Junction and Storage Temperature Range TJ, Tstg -55 150 °C 2
Lead Solder Temperature, Maximum TL 260 °C 10 second duration 2

CAD (KiCad official)

  • Symbol: SZMMBZ5V6ALT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: szmmbz5v6alt1g-etched.step / szmmbz5v6alt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); szmmbz5v6alt1g.step / szmmbz5v6alt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 30678a814b33b83d, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF