component
SY8892ARC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-563-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 4d ago |
| viewers | 4d ago |
| package.json | 4d ago |
| page.json | 4d ago |
| README.md | 4d ago |
| sy8892arc-etched.glb | 4d ago |
| sy8892arc-etched.step | 4d ago |
| sy8892arc-hero.glb | 4d ago |
| sy8892arc-hero.overlay.json | 4d ago |
| sy8892arc.glb | 4d ago |
| sy8892arc.kicad_mod | 4d ago |
| sy8892arc.kicad_sym | 4d ago |
| sy8892arc.lbr | 4d ago |
| sy8892arc.step | 4d ago |
SY8892ARC
Silergy Corp · DC-DC Converters · SOT-563-6
SY8892ARC from Silergy Corp, in a SOT-563-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Output feedback pin connected to the center point of the output resistor divider to program VOUT=0.6×(1+RH/RL). |
| 2 | GND | power_in | Ground pin. |
| 3 | VIN | power_in | Input supply pin (2.5V to 5.5V) that should be decoupled to GND with at least a 10µF ceramic capacitor. |
| 4 | LX | output | Inductor pin connected to the switching node of the inductor. |
| 5 | EN | input | Enable control that is pulled high to turn on and must not be left floating. |
| 6 | PG | output | Open-drain power good indicator that is low if the output is <90% or >120% of regulation voltage and high otherwise, with a pull-up resistor to the input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-563-6 |
| Category | Power Supply Chip |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | 5.5 | V | VIN = 5V, VOUT = 1.8V, L = 1.0μH, COUT = 22μF, TA = 25°C | 4 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | IOUT=1A, CCM | 4 |
| Input UVLO Threshold | VUVLO | 2.45 | 2.5 | V | 4 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | VEN=0V | 4 | |
| Supply Input Voltage (abs max) | -0.3 | 6 | V | 3 | |||
| FB, EN, PG Voltage | -0.3 | V | max is VIN + 0.6V | 3 | |||
| LX Voltage | -0.3 | 6 | V | Tested down to -3V <20ns; up to +7V <20ns | 3 | ||
| Power Dissipation | PD | 1.11 | W | TA = 25°C | 3 | ||
| Junction Temperature Range (abs max) | TJ | -40 | 150 | °C | 3 | ||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Supply Input Voltage (recommended) | 2.5 | 5.5 | V | 3 | |||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 3 | ||
| Thermal Resistance Junction-Ambient | θJA | 90 | °C/W | Natural convection, TA = 25°C, 2OZ two-layer Silergy evaluation board | 3 | ||
| Thermal Resistance Junction-Case | θJC | 20 | °C/W | Pin 4 is case position | 3 | ||
| Input UVLO Hysteresis | VYST | 150 | mV | 4 | |||
| Quiescent Current | IQ | 55 | µA | VFB=VREF×105% | 4 | ||
| LX Node Discharge Resistance | RDIS | 50 | Ω | 4 | |||
| Top FET RON | RDS(ON)1 | 125 | mΩ | 4 | |||
| Bottom FET RON | RDS(ON)2 | 75 | mΩ | 4 | |||
| EN Input Voltage High | VEN,H | 1.2 | V | 4 | |||
| EN Input Voltage Low | VEN,L | 0.4 | V | 4 | |||
| Switching Frequency | fSW | 1.5 | MHz | IOUT=1A, CCM | 4 | ||
| Top FET Current Limit | ILMT,TOP | 3 | A | 4 | |||
| Soft-start Time | tSS | 0.75 | ms | VOUT from 0% to 100% | 4 | ||
| Thermal Shutdown Temperature | TSD | 160 | °C | 4 | |||
| Thermal Shutdown Hysteresis | THYS | 20 | °C | 4 |
CAD (KiCad official)
- Symbol:
SY8892ARC - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563-6 (KiCad packages3D, STEP)
- 3D model files:
sy8892arc-etched.step/sy8892arc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8892arc.step/sy8892arc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (6 pp, sha256
b338da2f325b4534, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).