component
SY8513FCC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -37,6 +37,20 @@ SY8513FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracte - Footprint: `Package_SO:Diodes_SO-8EP` - 3D model: SOP-8-EP (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sy8513fcc.step`](sy8513fcc.step) | 194 KB | You want the bare part, or you mark your own boards. |+| [`sy8513fcc-etched.step`](sy8513fcc-etched.step) | 1.8 MB | You want the part with `SY8513FCC` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 446 faces against 63 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "sy8513fcc",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Silergy Corp DC-DC Converters, SOP-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+12−9@@ -4,7 +4,7 @@ "slug": "sy8513fcc", "title": "SY8513FCC", "brief": "Silergy Corp DC-DC Converters, SOP-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,7 +34,7 @@ "number": "1", "name": "IN", "type": "power_in",- "description": "Input supply pin, 4.5V to 100V range (abs max 100V). Decouple to GND with at least a 1\u03bcF ceramic capacitor placed close to the pin."+ "description": "Input supply pin, 4.5V to 100V range (abs max 100V). Decouple to GND with at least a 1μF ceramic capacitor placed close to the pin." }, { "number": "2",@@ -46,7 +46,7 @@ "number": "3", "name": "FS", "type": "input",- "description": "Switching frequency programming pin. Connect a resistor from FS to GND to set fSW between 100kHz and 500kHz per fSW(kHz) = 1e5 / RFS(k\u03a9). RFS range 200k\u03a9 to 1M\u03a9."+ "description": "Switching frequency programming pin. Connect a resistor from FS to GND to set fSW between 100kHz and 500kHz per fSW(kHz) = 1e5 / RFS(kΩ). RFS range 200kΩ to 1MΩ." }, { "number": "4",@@ -58,7 +58,7 @@ "number": "5", "name": "FB", "type": "input",- "description": "Output voltage feedback input to the error amplifier. Connect to the center tap of the output resistor divider to set VOUT = 0.8V \u00d7 (1 + R1/R2). VREF = 0.8V \u00b11%; IFB \u00b150nA."+ "description": "Output voltage feedback input to the error amplifier. Connect to the center tap of the output resistor divider to set VOUT = 0.8V × (1 + R1/R2). VREF = 0.8V ±1%; IFB ±50nA." }, { "number": "6",@@ -70,19 +70,19 @@ "number": "7", "name": "BS", "type": "passive",- "description": "Bootstrap capacitor pin supplying the high-side gate driver. Connect a 0.1\u03bcF ceramic capacitor between BS and LX. Abs max BS-LX = 6V."+ "description": "Bootstrap capacitor pin supplying the high-side gate driver. Connect a 0.1μF ceramic capacitor between BS and LX. Abs max BS-LX = 6V." }, { "number": "8", "name": "LX", "type": "output",- "description": "Switching node; drain of internal N-channel top FET (RDS(ON) 150m\u03a9). Connect to the external inductor and freewheeling Schottky diode. Handles up to 3A output; dynamic voltage rating VIN+3V to GND-5V for 10ns."+ "description": "Switching node; drain of internal N-channel top FET (RDS(ON) 150mΩ). Connect to the external inductor and freewheeling Schottky diode. Handles up to 3A output; dynamic voltage rating VIN+3V to GND-5V for 10ns." }, { "number": "9", "name": "EPAD", "type": "power_in",- "description": "Exposed thermal pad on the bottom of the SO8E package. Must be connected to the GND pin and to the system ground plane for optimal thermal performance (\u03b8JA = 42\u00b0C/W, \u03b8JC = 4\u00b0C/W).",+ "description": "Exposed thermal pad on the bottom of the SO8E package. Must be connected to the GND pin and to the system ground plane for optimal thermal performance (θJA = 42°C/W, θJC = 4°C/W).", "source": "renumbered-to-footprint-pad" } ],@@ -157,6 +157,9 @@ "docs/hero.png", "docs/sy8513fcc-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"- ]+ "viewers/footprint.html",+ "pads.json"+ ],+ "description": "Silergy Corp DC-DC Converters, SOP-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "visibility": "public" }