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docs sy8401abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sy8401abc: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md sy8401abc: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sy8401abc-etched.fit.json sy8401abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8401abc-etched.glb sy8401abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8401abc-etched.step sy8401abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8401abc.glb Publish 0.1.0 · Ray
sy8401abc.kicad_mod Publish 0.1.0 · Ray
sy8401abc.kicad_sym Publish 0.1.0 · Ray
sy8401abc.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sy8401abc.step Publish 0.1.0 · Ray

SY8401ABC

Silergy Corp · DC-DC Converters · SOT-23-6

SY8401ABC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BS passive Boot-strap pin supplying the high-side gate driver. Decouple to LX with a 100nF (0.1uF) low-ESR ceramic capacitor. Absolute maximum BS-LX = 4V.
2 GND power_in Ground pin. Also serves as the case position for θ_JC measurement on the SOT23-6 package; maximize copper area for best thermal and noise performance.
3 FB input Output feedback pin. Connect to the center of an external resistor divider to program the output voltage: VOUT = 0.6V × (1 + R1/R2). Reference voltage 0.594-0.606V; FB input current ±50nA max.
4 EN input Enable control. Pull high (>1.26V) to turn on, pull low (<0.94V) to shut down (I_SHDN < 10µA). Do not leave floating; consider a 1MΩ pull-down to GND if the driving source is high-impedance at shutdown.
5 IN power_in Input supply pin, 4.5V to 50V operating range (absolute maximum 55V). Decouple to GND with at least 1uF (10uF X5R low-ESR ceramic recommended) placed close to the IN/GND pins.
6 LX power_out Switching node / inductor pin. Connects internally to the drain of the high-side N-channel power FET (RDS(ON) = 700mΩ typ). Connect to the external inductor; minimize PCB copper area on this net to reduce EMI. Peak current limit 1.05-1.65A.

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOT-23-6
Category PMIC
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • SY8401ABC

CAD (KiCad official)

  • Symbol: SY8401ABC
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: sy8401abc-etched.step / sy8401abc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8401abc.step / sy8401abc.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sy8401abc.step 97 KB You want the bare part, or you mark your own boards.
sy8401abc-etched.step 1.9 MB You want the part with SY8401ABC already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 469 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (10 pp, sha256 5406cac6f9b1f5fd, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF