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docs sy8291abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sy8291abc: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md sy8291abc: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sy8291abc-etched.fit.json sy8291abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8291abc-etched.glb sy8291abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8291abc-etched.step sy8291abc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8291abc.glb Publish 0.1.0 · Ray
sy8291abc.kicad_mod Publish 0.1.0 · Ray
sy8291abc.kicad_sym Publish 0.1.0 · Ray
sy8291abc.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sy8291abc.step Publish 0.1.0 · Ray

SY8291ABC

Silergy Corp · DC-DC Converters · SOT-23-6

SY8291ABC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BS passive Boot-strap pin. Supplies the high-side gate driver via a bootstrap capacitor. Decouple to LX with a 0.1 µF (100 nF) ceramic cap. BS-to-LX voltage rating 3.6V absolute max (3.3V recommended).
2 GND power_in Device ground return. Also functions as the primary thermal path; maximize copper area for best thermal performance.
3 FB input Output feedback pin. Connect to the center of the R1/R2 resistor divider from VOUT to program the output: VOUT = 0.6 × (1 + R1/R2). Reference is 0.6V ±2%. FB absolute max 3.6V.
4 EN input Enable control input. Pull high to turn on the regulator; do not float. VENH ≈ 1.5V rising, VENL ≈ 0.4V falling. Absolute max EN voltage is VIN + 0.6V.
5 IN power_in Supply input pin. 5V to 40V operating range (42V absolute max). Decouple to GND with at least a 1 µF (4.7 µF recommended) low-ESR ceramic capacitor placed close to the pin.
6 LX power_out Inductor / switch node. Connect to the external inductor and the anode of the freewheeling Schottky diode. Internal N-channel power FET RDS(on) ≈ 180 mΩ; current limit ≈ 2A.

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOT-23-6
Category PMIC
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • SY8291ABC

CAD (KiCad official)

  • Symbol: SY8291ABC
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: sy8291abc-etched.step / sy8291abc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8291abc.step / sy8291abc.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sy8291abc.step 97 KB You want the bare part, or you mark your own boards.
sy8291abc-etched.step 2.0 MB You want the part with SY8291ABC already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 481 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (9 pp, sha256 e4d186cfba2c4177, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF