component
SY8290ABC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSY8290ABC
Silergy Corp · DC-DC Converters · SOT-23-6
SY8290ABC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin that supplies the high-side gate driver; decouple it to the LX pin with a 0.1uF ceramic capacitor. |
| 2 | GND | power_in | Ground pin. |
| 3 | FB | input | Output feedback pin; connect to the center point of the output resistor divider to set VOUT = 0.6*(1+R1/R2), with an absolute maximum FB voltage of 3.6V. |
| 4 | EN | input | Enable control; pull high to turn on the regulator and do not float the pin. |
| 5 | IN | power_in | Input pin supplying the regulator over 5V to 40V; decouple to GND with at least 1uF ceramic capacitance. |
| 6 | LX | output | Inductor pin; connect to the switching node of the output inductor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 5 | 40 | V | 3 | ||
| Input UVLO Threshold | VUVLO | 4.9 | V | Rising | 3 | ||
| Input UVLO Hysteresis | VUVLO_HYS | 200 | mV | 3 | |||
| Quiescent Current | IQ | 160 | µA | IOUT=0, VFB=VREF×105% | 3 | ||
| Shutdown Current | ISHDN | 10 | µA | EN=0 | 3 | ||
| Feedback Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | 3 | |
| FB Input Current | IFB | -50 | 10 | 50 | nA | VFB=VIN | 3 |
| Power FET RON | RDS(ON)1 | 2 | Ω | 3 | |||
| Power FET Current Limit | ILIM | 450 | mA | 3 | |||
| EN Rising Threshold | VENH | 1.5 | V | 3 | |||
| EN Falling Threshold | VENL | 0.4 | V | 3 | |||
| Minimum OFF Time | TOFF | 100 | ns | 3 | |||
| Minimum ON Time | TOFF | 100 | ns | 3 | |||
| Soft Start Time | Tss | 400 | us | 3 | |||
| Switching Frequency | FSW | 1.6 | 2 | 2.4 | MHz | 3 | |
| Thermal Shutdown Temperature | TSD | 150 | °C | 3 | |||
| Thermal Recovery Hysteresis | THYS | 15 | °C | 3 | |||
| Supply Input Voltage | 42 | V | 2 | ||||
| FB Voltage | 3.6 | V | 2 | ||||
| BS to LX Voltage | 3.6 | V | 2 | ||||
| Power Dissipation | PD | 0.4 | W | TA = 25°C, SOT23-6 | 2 | ||
| Package Thermal Resistance Junction-to-Ambient | θ JA | 250 | °C/W | 2 | |||
| Package Thermal Resistance Junction-to-Case | θ JC | 130 | °C/W | 2 | |||
| Junction Temperature Range (absolute maximum) | 150 | °C | 2 | ||||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Supply Input Voltage (recommended) | 5 | 40 | V | 2 | |||
| BS to LX Voltage (recommended) | 3.3 | V | 2 | ||||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range | -40 | 85 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin must | 7 |
CAD (KiCad official)
- Symbol:
SY8290ABC - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
sy8290abc-etched.step/sy8290abc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8290abc.step/sy8290abc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (8 pp, sha256
0d35bdc8cf1bd902, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).