# SY8253AIC

**Silergy Corp** · DC-DC Converters · TSOT-23-8

SY8253AIC from Silergy Corp, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | power_out | Boot-strap pin that supplies the high-side gate driver; decouple it to LX with a 0.1uF ceramic capacitor. |
| 2 | GND | power_in | Ground pin. |
| 3 | FB | input | Output feedback pin, connected to the center of the output resistor divider to set Vout = 0.6*(1+R1/R2). |
| 4 | SS | passive | Soft-start programming pin; a capacitor to ground sets Tss = Css*0.6V/4uA, and leaving it open gives the default 1ms soft-start. |
| 5 | PG | output | Power good indicator, open-drain output (SY8253AIC only). |
| 6 | EN | input | Enable control; pull high to turn on and do not float. |
| 7 | IN | power_in | Input pin; decouple to GND with at least 1uF ceramic capacitor, with input range 4.5V to 23V. |
| 8 | LX | output | Inductor pin; connect to the switching node of the inductor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 |  | 23 | V |  | 4 |
| Supply Input Voltage (recommended operating) | VIN | 4.5 |  | 23 | V |  | 3 |
| Junction Temperature Range (recommended operating) | TJ | -40 |  | 125 | °C |  | 3 |
| Ambient Temperature Range (recommended operating) | TA | -40 |  | 85 | °C |  | 3 |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V |  | 4 |
| FB Input Current | IFB | -50 |  | 50 | nA | VFB=3.3V | 4 |
| Top FET Peak Current Limit | ILIM,TOP | 5.1 | 6 | 6.9 | A |  | 4 |
| Bottom FET Valley Current Limit | ILIM,BOT | 3 | 3.7 | 4.5 | A |  | 4 |
| Shutdown Current | ISHDN |  | 5 | 10 | µA | EN=0 | 4 |
| Power Dissipation (TSOT23-8/TSOT23-6) | PD |  |  | 1.5 | W | TA = 25°C | 3 |
| Junction Temperature Range (absolute maximum) | TJ |  |  | 150 | °C |  | 3 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 3 |
| Lead Temperature (Soldering) | TLEAD |  |  | 260 | °C | 10 sec soldering | 3 |
| Package Thermal Resistance junction-to-ambient | θJA |  |  | 66 | °C/W | Natural convection, TA=25°C, two-layer Silergy EVB (Note 2) | 3 |
| Package Thermal Resistance junction-to-case | θJC |  |  | 15 | °C/W |  | 3 |
| Quiescent Current | IQ |  | 100 |  | µA | IOUT=0, VFB=VREF*105% | 4 |
| Top FET RON | RDS(ON)1 |  | 105 |  | mΩ |  | 4 |
| Bottom FET RON | RDS(ON)2 |  | 50 |  | mΩ |  | 4 |
| EN Rising Threshold | VENH |  | 1.5 |  | V |  | 4 |
| EN Falling Threshold | VENL |  | 0.4 |  | V |  | 4 |
| Power Good Threshold | VPG |  | 90 |  | %VREF | VFB falling, PG from high to low | 4 |
| Power Good Threshold | VPG |  | 95 |  | %VREF | VFB rising, PG from low to high | 4 |
| Power Good Threshold | VPG |  | 115 |  | %VREF | VFB rising, PG from high to low | 4 |
| Power Good Threshold | VPG |  | 110 |  | %VREF | VFB falling, PG from low to high | 4 |
| Power Good Delay Time (falling edge) | TPG_F |  | 10 |  | µs | PG falling edge | 4 |
| Power Good Delay Time (rising edge) | TPG_R |  | 60 |  | µs | PG rising edge | 4 |
| Output OVP Response Time | TOVP |  | 10 |  | µs |  | 4 |
| Output OVP Off Time | tOFF,OVP |  | 1000 |  | µs |  | 4 |
| Soft-start Charging Current | ISS |  | 4 |  | µA |  | 4 |
| Short Circuit Protection Wait Time | tWAIT,SCP |  | 1.9 |  | ms |  | 4 |
| Short Circuit Protection Off Time | tOFF,SCP |  | 15 |  | ms |  | 4 |
| Input UVLO Threshold | VUVLO |  | 4.5 |  | V |  | 4 |
| Input UVLO Hysteresis | VHYS |  | 0.3 |  | V |  | 4 |
| Min ON Time |  |  | 80 |  | ns |  | 4 |
| Min OFF Time |  |  | 160 |  | ns |  | 4 |
| Thermal Shutdown Temperature | TSD |  | 150 |  | ℃ |  | 4 |
| Thermal Shutdown Hysteresis | THYS |  | 15 |  | ℃ |  | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | 3) The PCB copper area associated with LX pin must | 9 |

## CAD (KiCad official)

- Symbol: `SY8253AIC`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-8`
- 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files: `sy8253aic-etched.step` / `sy8253aic-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy8253aic.step` / `sy8253aic.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Silergy Corp datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588901723998474240) (13 pp, sha256 `2580f7fc3ac98052`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sy8253aic-datasheet.pdf)