component
SY8253ADC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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sy8253adc: specified limits as data (metadata.characteristics, 31 rows from the datasheet)
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SY8253ADC
Silergy Corp · DC-DC Converters · SOT-23-6
SY8253ADC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin. Supplies the high-side gate driver. Decouple this pin to LX with a 0.1uF ceramic capacitor. |
| 2 | GND | power_in | Ground pin. Common return for power and signal. |
| 3 | FB | input | Output feedback pin. Connect to the center of the output resistor divider to program the output voltage: Vout = 0.6V × (1 + R1/R2). Internal reference 0.6V ±1.5%. |
| 4 | EN | input | Enable control input. Pull high (>1.5V rising threshold) to turn the regulator on; below 0.4V it is off. Do not float. |
| 5 | IN | power_in | Input supply pin, 4.5V to 23V. Decouple to GND with at least a 1uF ceramic capacitor placed close to the pin. |
| 6 | LX | power_out | Switching node. Connect to the external inductor. Internal top/bottom FETs switch this node at 500 kHz with 3A output capability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
SY8253ADCSY8253ADCAIC
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 23 | V | 4 | ||
| Shutdown Current | ISHDN | 5 | 10 | µA | EN=0 | 4 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 4 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=3.3V | 4 | |
| Top FET Peak Current Limit | ILIM,TOP | 5.1 | 6 | 6.9 | A | 4 | |
| Bottom FET Valley Current Limit | ILIM,BOT | 3 | 3.7 | 4.5 | A | 4 | |
| Power Dissipation | PD | 1.5 | W | TA = 25°C, TSOT23-8 /TSOT23-6 | 3 | ||
| Junction Temperature Range (absolute maximum) | 150 | °C | 3 | ||||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Supply Input Voltage (recommended) | 4.5 | 23 | V | 3 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range (recommended) | -40 | 85 | °C | 3 | |||
| Quiescent Current | IQ | 100 | µA | IOUT=0, VFB=VREF*105% | 4 | ||
| Top FET RON | RDS(ON)1 | 105 | mΩ | 4 | |||
| Bottom FET RON | RDS(ON)2 | 50 | mΩ | 4 | |||
| EN Rising Threshold | VENH | 1.5 | V | 4 | |||
| EN Falling Threshold | VENL | 0.4 | V | 4 | |||
| Output OVP Response Time | TOVP | 10 | µs | 4 | |||
| Output OVP Off Time | tOFF,OVP | 1000 | µs | 4 | |||
| Soft-start Charging Current | ISS | 4 | µA | 4 | |||
| Short Circuit Protection Wait Time | tWAIT,SCP | 1.9 | ms | 4 | |||
| Short Circuit Protection Off Time | tOFF,SCP | 15 | ms | 4 | |||
| Input UVLO Threshold | VUVLO | 4.5 | V | 4 | |||
| Input UVLO Hysteresis | VHYS | 0.3 | V | 4 | |||
| Min ON Time | 80 | ns | 4 | ||||
| Min OFF Time | 160 | ns | 4 | ||||
| Thermal Shutdown Temperature | TSD | 150 | ℃ | 4 | |||
| Thermal Shutdown Hysteresis | THYS | 15 | ℃ | 4 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 66 | °C/W | Natural convection at TA = 25°C on two-layer Silergy Evaluation Board (Note 2) | 3 | ||
| Package Thermal Resistance, junction-to-case | θJC | 15 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
SY8253ADC - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
sy8253adc-etched.step/sy8253adc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8253adc.step/sy8253adc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (13 pp, sha256
a5a2858a74928804, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SY8253ADC
**Silergy Corp** · DC-DC Converters · SOT-23-6
SY8253ADC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin. Supplies the high-side gate driver. Decouple this pin to LX with a 0.1uF ceramic capacitor. |
| 2 | GND | power_in | Ground pin. Common return for power and signal. |
| 3 | FB | input | Output feedback pin. Connect to the center of the output resistor divider to program the output voltage: Vout = 0.6V × (1 + R1/R2). Internal reference 0.6V ±1.5%. |
| 4 | EN | input | Enable control input. Pull high (>1.5V rising threshold) to turn the regulator on; below 0.4V it is off. Do not float. |
| 5 | IN | power_in | Input supply pin, 4.5V to 23V. Decouple to GND with at least a 1uF ceramic capacitor placed close to the pin. |
| 6 | LX | power_out | Switching node. Connect to the external inductor. Internal top/bottom FETs switch this node at 500 kHz with 3A output capability. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |
## Ordering variants
Same part, different packaging or reel option.
- `SY8253ADC`
- `SY8253ADCAIC`
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | | 23 | V | | 4 |
| Shutdown Current | ISHDN | | 5 | 10 | µA | EN=0 | 4 |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | | 4 |
| FB Input Current | IFB | -50 | | 50 | nA | VFB=3.3V | 4 |
| Top FET Peak Current Limit | ILIM,TOP | 5.1 | 6 | 6.9 | A | | 4 |
| Bottom FET Valley Current Limit | ILIM,BOT | 3 | 3.7 | 4.5 | A | | 4 |
| Power Dissipation | PD | | | 1.5 | W | TA = 25°C, TSOT23-8 /TSOT23-6 | 3 |
| Junction Temperature Range (absolute maximum) | | | | 150 | °C | | 3 |
| Lead Temperature (Soldering) | | | | 260 | °C | Soldering, 10 sec. | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Supply Input Voltage (recommended) | | 4.5 | | 23 | V | | 3 |
| Junction Temperature Range (recommended) | | -40 | | 125 | °C | | 3 |
| Ambient Temperature Range (recommended) | | -40 | | 85 | °C | | 3 |
| Quiescent Current | IQ | | 100 | | µA | IOUT=0, VFB=VREF*105% | 4 |
| Top FET RON | RDS(ON)1 | | 105 | | mΩ | | 4 |
| Bottom FET RON | RDS(ON)2 | | 50 | | mΩ | | 4 |
| EN Rising Threshold | VENH | | 1.5 | | V | | 4 |
| EN Falling Threshold | VENL | | 0.4 | | V | | 4 |
| Output OVP Response Time | TOVP | | 10 | | µs | | 4 |
| Output OVP Off Time | tOFF,OVP | | 1000 | | µs | | 4 |
| Soft-start Charging Current | ISS | | 4 | | µA | | 4 |
| Short Circuit Protection Wait Time | tWAIT,SCP | | 1.9 | | ms | | 4 |
| Short Circuit Protection Off Time | tOFF,SCP | | 15 | | ms | | 4 |
| Input UVLO Threshold | VUVLO | | 4.5 | | V | | 4 |
| Input UVLO Hysteresis | VHYS | | 0.3 | | V | | 4 |
| Min ON Time | | | 80 | | ns | | 4 |
| Min OFF Time | | | 160 | | ns | | 4 |
| Thermal Shutdown Temperature | TSD | | 150 | | ℃ | | 4 |
| Thermal Shutdown Hysteresis | THYS | | 15 | | ℃ | | 4 |
| Package Thermal Resistance, junction-to-ambient | θJA | | 66 | | °C/W | Natural convection at TA = 25°C on two-layer Silergy Evaluation Board (Note 2) | 3 |
| Package Thermal Resistance, junction-to-case | θJC | | 15 | | °C/W | | 3 |
## CAD (KiCad official)
- Symbol: `SY8253ADC`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `sy8253adc-etched.step` / `sy8253adc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy8253adc.step` / `sy8253adc.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](docs/sy8253adc-datasheet.pdf) (13 pp, sha256 `a5a2858a74928804`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sy8253adc-datasheet.pdf)