component

SY8156IADC

Public Made by Adom

by adom

Silergy Corp DC-DC Converters, TSOT23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)sy8156iadcfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4h ago
viewers sy8156iadc: viewers · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago
sy8156iadc-etched.glb Publish 0.1.0 · Ray 4h ago
sy8156iadc-etched.step sy8156iadc: factory component page (tier=lcsc) · Ray 4h ago
sy8156iadc-hero.glb sy8156iadc: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
sy8156iadc-hero.overlay.json Publish 0.1.0 · Ray 4h ago
sy8156iadc.glb Publish 0.1.0 · Ray 4h ago
sy8156iadc.kicad_mod Publish 0.1.0 · Ray 4h ago
sy8156iadc.kicad_sym Publish 0.1.0 · Ray 4h ago
sy8156iadc.lbr Publish 0.1.0 · Ray 4h ago
sy8156iadc.step Publish 0.1.0 · Ray 4h ago

SY8156IADC

Silergy Corp · DC-DC Converters · TSOT23-6

SY8156IADC from Silergy Corp, in a TSOT23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Feedback pin, connected to the center of the output resistor divider to set VOUT = 0.6×(1+RH/RL), with VREF of 591 mV to 609 mV (600 mV typ).
2 EN input Enable control pin, pulled high to turn the device on (rising threshold 1.08 V to 1.32 V) and must not be left floating.
3 GND power_in Power ground pin.
4 IN power_in Input supply pin, operating from 4.5 V to 18 V, to be decoupled to GND with at least a 10 µF ceramic capacitor.
5 LX output Inductor pin connected to the switching node; absolute dynamic voltage in 10 ns is limited to IN+3 V to GND-5 V.
6 BS passive Boot-strap pin supplying the high-side gate driver, connected through a 0.1 µF ceramic capacitor to LX, with BS-LX voltage limited to -0.3 V to 4 V.

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package TSOT23-6
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 4.5 18 V 3
Quiescent Current IQ 200 µA IOUT=0, VFB=VREF×105% 3
Shutdown Current ISHDN 5 10 µA EN=0 3
Feedback Reference Voltage VREF 591 600 609 mV 3
FB Input Current IFB -50 50 nA VFB=3.3V 3
EN Rising Threshold VEN,R 1.08 1.2 1.32 V 3
EN Falling Threshold VEN,F 0.9 1 1.1 V 3
Supply Input Voltage (absolute maximum) -0.3 19 V 2
LX, EN Voltage -0.3 V Printed maximum is VIN + 0.3V (not numeric) 2
FB, BS-LX Voltage -0.3 4 V 2
Power Dissipation TSOT23-6 PD 2.1 W TA = 25°C 2
Junction Temperature Range (absolute maximum) -40 150 °C 2
Lead Temperature (Soldering) 260 °C 10 sec. 2
Storage Temperature Range -65 150 °C 2
Supply Input Voltage (recommended) 4.5 18 V 2
Junction Temperature Range (recommended) -40 125 °C 2
Ambient Temperature Range -40 85 °C 2
UVLO Threshold VUVLO 4.5 V 3
UVLO Hysteresis VHYS 0.3 V 3
Output Discharge Resistance RDIS 50 Ω 3
Top FET RON RDS(ON)1 29 mΩ 3
Bottom FET RON RDS(ON)2 19 mΩ 3
Min ON Time tON,MIN 50 ns 3
Min OFF Time tOFF,MIN 100 ns 3
Soft-start Time tSS 1 ms 3
Switching Frequency fSW 400 kHz VOUT=3.3V, CCM 3
Top FET Current Limit ILIM,TOP 8 A 3
Bottom FET Current Limit ILIM,BOT 6 A 3
Output Under Voltage Protection Threshold VUVP 0.33 VREF 3
Output UVP Delay tUVP,DLY 100 µs 3
UVP Hiccup On Time tUVP,ON 2.5 ms 3
UVP Hiccup Off Time tUVP,OFF 9 ms 3
Thermal Shutdown Temperature TSD 150 °C 3
Thermal Shutdown Hysteresis THYS 15 °C 3
Package Thermal Resistance Junction-to-Ambient θJA 46 °C/W Note 2: natural convection at TA = 25°C, 2OZ two-layer Silergy evaluation board 2
Package Thermal Resistance Junction-to-Case θJC 6 °C/W Note 2: paddle of TSOT23-6 is the case position 2

CAD (KiCad official)

  • Symbol: SY8156IADC
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: TSOT23-6 (KiCad packages3D, STEP)
  • 3D model files: sy8156iadc-etched.step / sy8156iadc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8156iadc.step / sy8156iadc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (5 pp, sha256 e57c0143ebfac301, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF