component
SY8113ADC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
| sy8113adc-etched.glb | 16d ago |
| sy8113adc-etched.step | 16d ago |
| sy8113adc-hero.glb | 16d ago |
| sy8113adc-hero.overlay.json | 16d ago |
| sy8113adc.glb | 16d ago |
| sy8113adc.kicad_mod | 16d ago |
| sy8113adc.kicad_sym | 16d ago |
| sy8113adc.lbr | 16d ago |
| sy8113adc.step | 16d ago |
SY8113ADC
Silergy Corp · DC-DC Converters · TSOT-23-6
SY8113ADC from Silergy Corp, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin supplying the high side gate driver; decouple to the LX pin with a 0.1uF ceramic capacitor. |
| 2 | GND | power_in | Ground pin. |
| 3 | FB | input | Output feedback pin connected to the center of the output resistor divider to program Vout=0.6*(1+R1/R2), with 0.6V reference. |
| 4 | EN | input | Enable control; pull high to turn on and do not float (rising threshold 1.5V, falling threshold 0.4V). |
| 5 | IN | power_in | Input supply pin, 4.5V to 18V operating range; decouple to GND with at least 1uF ceramic capacitor. |
| 6 | LX | output | Inductor pin connected to the switching node of the inductor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-6 |
| Category | Power Management ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 18 | V | 3 | ||
| Shutdown Current | ISHDN | 5 | 10 | µA | EN=0 | 3 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 3 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=3.3V | 3 | |
| Top FET RON | RDS(ON)1 | 80 | 90 | mΩ | 3 | ||
| Bottom FET RON | RDS(ON)2 | 40 | 50 | mΩ | 3 | ||
| Bottom FET Valley Current Limit | ILIM | 3 | 4.25 | A | 3 | ||
| On Time | TON | 150 | 200 | 250 | ns | VIN = 12V ,VOUT=1.2V, IOUT = 1A | 3 |
| Min ON Time | 50 | 80 | 120 | ns | 3 | ||
| Min OFF Time | 140 | 170 | 220 | ns | 3 | ||
| Supply Input Voltage (abs max) | 19 | V | 2 | ||||
| FB Voltage (abs max) | 4 | V | 2 | ||||
| Power Dissipation | PD | 1 | W | TA = 25°C, TSOT23-6(FC) | 2 | ||
| Junction Temperature (abs max) | 125 | °C | 2 | ||||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Supply Input Voltage (recommended) | 4.5 | 18 | V | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range | -40 | 85 | °C | 2 | |||
| Thermal Resistance Junction to Ambient | θJA | 100 | °C/W | Note 2 | 2 | ||
| Thermal Resistance Junction to Case | θJC | 11.2 | °C/W | Note 2 | 2 | ||
| Quiescent Current | IQ | 100 | µA | IOUT=0, VFB=VREF*105% | 3 | ||
| EN Rising Threshold | VENH | 1.5 | V | 3 | |||
| EN Falling Threshold | VENL | 0.4 | V | 3 | |||
| Input UVLO Threshold | VUVLO | 4.5 | V | 3 | |||
| UVLO Hysteresis | VHYS | 0.3 | V | 3 | |||
| Switching Frequency | 500 | kHz | 3 | ||||
| Soft-start Time | tSS | 800 | uS | 3 | |||
| Thermal Shutdown Temperature | TSD | 150 | °C | 3 | |||
| Thermal Shutdown Hysteresis | THYS | 15 | °C | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin must | 8 |
CAD (KiCad official)
- Symbol:
SY8113ADC - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
sy8113adc-etched.step/sy8113adc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8113adc.step/sy8113adc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (10 pp, sha256
36378f186fc359c6, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).