component
SY8105ADC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
| sy8105adc-etched.glb | 17d ago |
| sy8105adc-etched.step | 17d ago |
| sy8105adc-hero.glb | 17d ago |
| sy8105adc-hero.overlay.json | 17d ago |
| sy8105adc.glb | 17d ago |
| sy8105adc.kicad_mod | 17d ago |
| sy8105adc.kicad_sym | 17d ago |
| sy8105adc.lbr | 17d ago |
| sy8105adc.step | 17d ago |
SY8105ADC
Silergy Corp · DC-DC Converters · TSOT-23-6
SY8105ADC from Silergy Corp, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Output feedback pin, connected to the center point of the output resistor divider to program the output voltage as Vout = 0.6 × (1 + R1/R2). |
| 2 | EN | input | Enable control pin that must be pulled high to turn the device on and must not be left floating. |
| 3 | GND | power_in | Ground pin. |
| 4 | IN | power_in | Input supply pin, to be decoupled to GND with at least 1 µF ceramic capacitor; the recommended supply input range is 4.5 V to 18 V. |
| 5 | LX | output | Inductor pin, connected to the switching node of the inductor. |
| 6 | BS | passive | Boot-strap pin supplying the high-side gate driver, to be decoupled to the LX pin with a 0.1 µF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 18 | V | 4 | ||
| Shutdown Current | ISHDN | 5 | 10 | µA | EN=0 | 4 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 4 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=3.3V | 4 | |
| Supply Input Voltage (absolute maximum) | 19 | V | 2 | ||||
| FB Voltage (absolute maximum) | 4 | V | 2 | ||||
| Power Dissipation | PD | 1.75 | W | TA = 25°C, TSOT23-6(FC) | 2 | ||
| Junction Temperature Range (absolute maximum) | 125 | °C | 2 | ||||
| Lead Temperature | 260 | °C | Soldering, 10 sec | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Supply Input Voltage (recommended) | 4.5 | 18 | V | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range | -40 | 85 | °C | 2 | |||
| Quiescent Current | IQ | 100 | µA | IOUT=0, VFB=VREF*105% | 4 | ||
| Top FET RON | RDS(ON)1 | 40 | mΩ | 4 | |||
| Bottom FET RON | RDS(ON)2 | 20 | mΩ | 4 | |||
| TOP FET Peak Current Limit | ILIM,TOP | 10 | A | 4 | |||
| Bottom FET Valley Current Limit | ILIM,BOTTOM | 5 | A | 4 | |||
| EN Rising Threshold | VENH | 1.5 | V | 4 | |||
| EN Falling Threshold | VENL | 0.4 | V | 4 | |||
| Input UVLO Threshold | VUVLO | 4.5 | V | 4 | |||
| UVLO Hysteresis | VHYS | 0.3 | V | 4 | |||
| Min ON Time | 80 | ns | 4 | ||||
| Min OFF Time | 160 | ns | 4 | ||||
| Switching Frequency | 500 | kHz | 4 | ||||
| Thermal Shutdown Temperature | TSD | 150 | °C | 4 | |||
| Thermal Shutdown Hysteresis | THYS | 15 | °C | 4 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 56 | °C/W | Natural convection, TA = 25°C, two-layer Silergy evaluation board (Note 2) | 2 | ||
| Package Thermal Resistance, junction-to-case | θJC | 6.3 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin must be | 8 |
CAD (KiCad official)
- Symbol:
SY8105ADC - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
sy8105adc-etched.step/sy8105adc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8105adc.step/sy8105adc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (11 pp, sha256
634bd70a01332d63, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).