component
SY8104ADC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SY8104ADC
Silergy Corp · DC-DC Converters · TSOT-23-6
SY8104ADC from Silergy Corp, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin connected to the center point of the output resistor divider to program Vout = 0.6*(1+R1/R2). |
| 2 | EN | input | Enable control pin that must be pulled high to turn the device on and must not float; the datasheet gives EN falling threshold 0.4V and rising threshold 1.5V. |
| 3 | GND | power_in | Ground pin, to be connected to a maximized PCB copper area for best thermal and noise performance. |
| 4 | IN | power_in | Input supply pin, to be decoupled to the GND pin with at least 1uF ceramic capacitor, with the input range 4.5V to 18V. |
| 5 | LX | output | Inductor pin connected to the switching node of the inductor, with dynamic LX voltage limited to IN+3V to GND-5V for 10ns. |
| 6 | BS | passive | Bootstrap pin supplying the high-side gate driver, to be decoupled to the LX pin with a 0.1uF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-6 |
| Category | Power Management ICs |
| Pins | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin must | 8 |
CAD (KiCad official)
- Symbol:
SY8104ADC - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
sy8104adc-etched.step/sy8104adc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8104adc.step/sy8104adc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (10 pp, sha256
46dbeab9a3b07308, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SY8104ADC
**Silergy Corp** · DC-DC Converters · TSOT-23-6
SY8104ADC from Silergy Corp, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin connected to the center point of the output resistor divider to program Vout = 0.6*(1+R1/R2). |
| 2 | EN | input | Enable control pin that must be pulled high to turn the device on and must not float; the datasheet gives EN falling threshold 0.4V and rising threshold 1.5V. |
| 3 | GND | power_in | Ground pin, to be connected to a maximized PCB copper area for best thermal and noise performance. |
| 4 | IN | power_in | Input supply pin, to be decoupled to the GND pin with at least 1uF ceramic capacitor, with the input range 4.5V to 18V. |
| 5 | LX | output | Inductor pin connected to the switching node of the inductor, with dynamic LX voltage limited to IN+3V to GND-5V for 10ns. |
| 6 | BS | passive | Bootstrap pin supplying the high-side gate driver, to be decoupled to the LX pin with a 0.1uF ceramic capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-6 |
| Category | Power Management ICs |
| Pins | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | 3) The PCB copper area associated with LX pin must | 8 |
## CAD (KiCad official)
- Symbol: `SY8104ADC`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `sy8104adc-etched.step` / `sy8104adc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy8104adc.step` / `sy8104adc.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](docs/sy8104adc-datasheet.pdf) (10 pp, sha256 `46dbeab9a3b07308`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sy8104adc-datasheet.pdf)