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docs sy8089a1aac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sy8089a1aac: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md sy8089a1aac: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sy8089a1aac-etched.fit.json sy8089a1aac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8089a1aac-etched.glb sy8089a1aac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8089a1aac-etched.step sy8089a1aac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8089a1aac.glb Publish 0.1.0 · Ray
sy8089a1aac.kicad_mod Publish 0.1.0 · Ray
sy8089a1aac.kicad_sym Publish 0.1.0 · Ray
sy8089a1aac.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sy8089a1aac.step Publish 0.1.0 · Ray

SY8089A1AAC

Silergy Corp · DC-DC Converters · SOT-23-5

SY8089A1AAC from Silergy Corp, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable control input. Pull high (VEN,H ≥ 1.2V) to turn on the regulator; drive low (VEN,L ≤ 0.4V) to shut down (ISHDN ~0.1µA). Do not leave floating; add a 1MΩ pull-down to GND if driven by a high-Z source.
2 GND power_in Ground reference for the IC. Connect to the system ground plane with a low-impedance path; the CIN loop between IN and GND must be minimized.
3 LX output Switching node output of the internal high-side/low-side FET bridge. Connect to the external inductor (e.g. 1.0µH). Rated -0.3V to 6.0V (transient -3V/+7V <40ns). Minimize PCB copper area on this net to reduce EMI.
4 IN power_in Power supply input, 2.5V to 5.5V (abs max 6.0V). Decouple to GND with at least a 10µF X5R (or better) ≥6.3V ceramic capacitor placed close to the pin.
5 FB input Output voltage feedback input. Connect to the midpoint of the RH/RL divider from VOUT to GND to program VOUT = 0.6V × (1 + RH/RL). Internal reference is 600mV (591-609mV). A feed-forward cap (e.g. 22pF) across RH improves transient response.

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SY8089A1AAC

CAD (KiCad official)

  • Symbol: SY8089A1AAC
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: sy8089a1aac-etched.step / sy8089a1aac-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8089a1aac.step / sy8089a1aac.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sy8089a1aac.step 85 KB You want the bare part, or you mark your own boards.
sy8089a1aac-etched.step 2.2 MB You want the part with SY8089A1AAC already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 539 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (10 pp, sha256 8587214d50cc945a, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF