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SY8088IAAC

Public Made by Adom

by adom

Silergy Corp DC-DC Converters, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sy8088iaac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sy8088iaac: specified limits as data (metadata.characteristics, 29 rows from the datasheet) · Ray
README.md sy8088iaac: specified limits as data (metadata.characteristics, 29 rows from the datasheet) · Ray
sy8088iaac-etched.fit.json sy8088iaac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8088iaac-etched.glb sy8088iaac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8088iaac-etched.step sy8088iaac: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8088iaac.glb Publish 0.1.0 · Ray
sy8088iaac.kicad_mod Publish 0.1.0 · Ray
sy8088iaac.kicad_sym Publish 0.1.0 · Ray
sy8088iaac.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sy8088iaac.step Publish 0.1.0 · Ray

SY8088IAAC

Silergy Corp · DC-DC Converters · SOT-23-5

SY8088IAAC from Silergy Corp, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable control input. Pull high (>1.2V) to turn on the regulator; pull low (<0.4V) to shut down (ISHDN ~0.1µA). Do not leave floating. Absolute max = VIN + 0.6V.
2 GND power_in Ground reference for the IC. Also serves as the return for the internal synchronous (low-side) MOSFET. Case position used for θJC measurement is pin 3; GND should have maximized copper for thermal performance.
3 LX output Switching node. Connect to the external inductor. Internal top/bottom power MOSFETs (260mΩ / 170mΩ RDS(ON)) drive this node at 1.5MHz. Also provides output auto-discharge via ~50Ω RDIS when disabled. Absolute max −0.3V to 6.0V.
4 IN power_in Supply input pin, 2.5V to 5.5V operating range (6.0V absolute max). Decouple to GND with at least a 10µF X5R (or better) ceramic capacitor placed close to the pin.
5 FB input Output feedback input. Connect to the center of an external resistor divider (RH/RL) from VOUT to GND to program the output voltage: VOUT = 0.6 × (1 + RH/RL). Internal reference VREF = 0.6V typ. Absolute max = VIN + 0.6V.

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SY8088IAAC

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Input Voltage 6 V 3
LX Voltage -0.3 6 V LX voltage tested down to -3V <40ns (*1); up to +7V <40ns (*2) 3
Power Dissipation PD 0.77 W TA = 25°C 3
Junction Temperature Range -40 150 °C 3
Lead Temperature (Soldering, 10 sec.) 260 °C Soldering, 10 sec. 3
Storage Temperature Range 150 °C 3
Supply Input Voltage 2.5 5.5 V 3
Junction Temperature Range -40 125 °C 3
Ambient Temperature Range -40 85 °C 3
Input Voltage Range VIN 2.5 5.5 V 4
Quiescent Current IQ 50 70 µA VFB=VREF×105% 4
Shutdown Current ISHDN 0.1 1 µA VEN=0V 4
Feedback Reference Voltage VREF 591 600 mV IOUT=0.5A, CCM 4
EN Input Voltage High VEN,H 1.2 V 4
EN Input Voltage Low VEN,L 0.4 V 4
Maximum Duty Cycle DMAX 100 % 4
Top FET Current Limit ILMT,TOP 1.5 2.5 A 4
Thermal Resistance Junction-to-Ambient θJA 130 °C/W Natural convection, TA = 25°C, 2OZ two-layer Silergy evaluation board (Note 2) 3
Thermal Resistance Junction-to-Case θJC 28 °C/W Pin 3 is the case position for θJC measurement (Note 2) 3
Input UVLO Threshold VUVLO 2.45 V 4
Input UVLO Hysteresis VHYS 150 mV 4
LX Node Discharge Resistance RDIS 50 Ω 4
Top FET RON RDS(ON)1 260 mΩ 4
Min ON Time tON,MIN 60 ns 4
Turn On Delay tON,DLY 300 µs 4
Soft-start Time tSS 700 us 4
Switching Frequency fSW 1.5 MHz IOUT=0.5A, CCM 4
Thermal Shutdown Temperature TSD 160 °C 4
Thermal Shutdown Hysteresis THYS 20 °C 4

CAD (KiCad official)

  • Symbol: SY8088IAAC
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: sy8088iaac-etched.step / sy8088iaac-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8088iaac.step / sy8088iaac.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sy8088iaac.step 85 KB You want the bare part, or you mark your own boards.
sy8088iaac-etched.step 2.2 MB You want the part with SY8088IAAC already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 531 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (10 pp, sha256 058fdba118f3f436, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF