component
SY8047QDC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, TQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SY8047QDC
Silergy Corp · DC-DC Converters · TQFN-16-EP(3x3)
SY8047QDC from Silergy Corp, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX | output | Inductor pin; connect this pin to the switching node of the inductor. |
| 2 | LX | output | Inductor pin; connect this pin to the switching node of the inductor. |
| 3 | NC | unconnected | No connection. |
| 4 | PG | output | Open-drain power good indicator: low if the output is below 90% of the regulation voltage, high otherwise; connect a pull-up resistor to the input. |
| 5 | FB | input | Output feedback pin; connect to the center point of the output resistor divider to program VOUT = 0.6V*(1+RH/RL), with VREF of 0.591V to 0.609V. |
| 6 | AGND | power_in | Analog ground pin. |
| 7 | NC | unconnected | No connection. |
| 8 | NC | unconnected | No connection. |
| 9 | SS | passive | Soft-start programming pin; do not float; connect a capacitor to ground so that tSS = Max(60µs, CSS×0.6V/1.6µA). |
| 10 | SVIN | power_in | Supply voltage for the control circuit; decouple to ground with at least 1uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 11 | PVIN | power_in | Supply voltage for the power circuit; decouple to ground with at least 22uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 12 | PVIN | power_in | Supply voltage for the power circuit; decouple to ground with at least 22uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 13 | EN | input | Enable input with integrated 4MΩ pull-down resistor; EN rising threshold is 1.5V and falling threshold is 0.4V. |
| 14 | PGND | power_in | Power ground pin. |
| 15 | PGND | power_in | Power ground pin. |
| 16 | NC | unconnected | No connection. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | 5.5 | V | 3 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN=0 | 3 | |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 3 | |
| Supply Input Voltage | 2.5 | 5.5 | V | 2 | |||
| Junction Temperature Range | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range | -40 | 85 | °C | 2 | |||
| All pins voltage | 6 | V | 2 | ||||
| Power Dissipation | PD | 2.6 | W | TA = 25°C, QFN3x3 | 2 | ||
| Junction Temperature Range | 150 | °C | 2 | ||||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | 2 | ||||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 38 | °C/W | JEDEC 51-3 low-conductivity single-layer board, natural convection, TA = 25°C | 2 | ||
| Package Thermal Resistance, junction-to-case | θJC | 8 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
SY8047QDC - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
sy8047qdc-etched.step/sy8047qdc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8047qdc.step/sy8047qdc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (6 pp, sha256
35a9f476df657f9b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SY8047QDC
**Silergy Corp** · DC-DC Converters · TQFN-16-EP(3x3)
SY8047QDC from Silergy Corp, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX | output | Inductor pin; connect this pin to the switching node of the inductor. |
| 2 | LX | output | Inductor pin; connect this pin to the switching node of the inductor. |
| 3 | NC | unconnected | No connection. |
| 4 | PG | output | Open-drain power good indicator: low if the output is below 90% of the regulation voltage, high otherwise; connect a pull-up resistor to the input. |
| 5 | FB | input | Output feedback pin; connect to the center point of the output resistor divider to program VOUT = 0.6V*(1+RH/RL), with VREF of 0.591V to 0.609V. |
| 6 | AGND | power_in | Analog ground pin. |
| 7 | NC | unconnected | No connection. |
| 8 | NC | unconnected | No connection. |
| 9 | SS | passive | Soft-start programming pin; do not float; connect a capacitor to ground so that tSS = Max(60µs, CSS×0.6V/1.6µA). |
| 10 | SVIN | power_in | Supply voltage for the control circuit; decouple to ground with at least 1uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 11 | PVIN | power_in | Supply voltage for the power circuit; decouple to ground with at least 22uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 12 | PVIN | power_in | Supply voltage for the power circuit; decouple to ground with at least 22uF ceramic capacitor. Input range is 2.5V to 5.5V. |
| 13 | EN | input | Enable input with integrated 4MΩ pull-down resistor; EN rising threshold is 1.5V and falling threshold is 0.4V. |
| 14 | PGND | power_in | Power ground pin. |
| 15 | PGND | power_in | Power ground pin. |
| 16 | NC | unconnected | No connection. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | | 5.5 | V | | 3 |
| Shutdown Current | ISHDN | | 0.1 | 1 | µA | EN=0 | 3 |
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | | 3 |
| Supply Input Voltage | | 2.5 | | 5.5 | V | | 2 |
| Junction Temperature Range | | -40 | | 125 | °C | | 2 |
| Ambient Temperature Range | | -40 | | 85 | °C | | 2 |
| All pins voltage | | | | 6 | V | | 2 |
| Power Dissipation | PD | | | 2.6 | W | TA = 25°C, QFN3x3 | 2 |
| Junction Temperature Range | | | | 150 | °C | | 2 |
| Lead Temperature (Soldering, 10 sec.) | | | | 260 | °C | | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Package Thermal Resistance, junction-to-ambient | θJA | | 38 | | °C/W | JEDEC 51-3 low-conductivity single-layer board, natural convection, TA = 25°C | 2 |
| Package Thermal Resistance, junction-to-case | θJC | | 8 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `SY8047QDC`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `sy8047qdc-etched.step` / `sy8047qdc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy8047qdc.step` / `sy8047qdc.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234664750653440) (6 pp, sha256 `35a9f476df657f9b`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sy8047qdc-datasheet.pdf)