component
SY8035DBC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
| sy8035dbc-etched.glb | 7d ago |
| sy8035dbc-etched.step | 7d ago |
| sy8035dbc-hero.glb | 7d ago |
| sy8035dbc-hero.overlay.json | 7d ago |
| sy8035dbc.glb | 7d ago |
| sy8035dbc.kicad_mod | 7d ago |
| sy8035dbc.kicad_sym | 7d ago |
| sy8035dbc.lbr | 7d ago |
| sy8035dbc.step | 7d ago |
SY8035DBC
Silergy Corp · DC-DC Converters · DFN-10(3x3)
SY8035DBC from Silergy Corp, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX | output | Phase node pin that connects to the inductor; its PCB copper area should be kept as small as possible to improve noise immunity. |
| 2 | LX | output | Phase node pin that connects to the inductor; its PCB copper area should be kept as small as possible to improve noise immunity. |
| 3 | LX | output | Phase node pin that connects to the inductor; its PCB copper area should be kept as small as possible to improve noise immunity. |
| 4 | PG | output | Open-drain power-good output that is low when the output is below 90% of the regulation voltage and high otherwise, and needs a pull-up resistor (above 100k) to the input. |
| 5 | EN | input | Enable control that turns the device on when pulled high (above 1.5V) and shuts it down when below 0.4V, with an integrated 1MΩ pull-down resistor. |
| 6 | FB | input | Output feedback input that connects to the center of the output resistor divider, with VOUT = 0.6×(1+R1/R2). |
| 7 | SS | passive | Soft-start programming pin; a capacitor from this pin to ground sets the soft-start time as tSS = max(600µs, CSS×0.6V/10µA). |
| 8 | SVIN | power_in | Signal power input that must be decoupled to GND with at least a 1µF ceramic capacitor. |
| 9 | PVIN | power_in | Power input (2.7V to 5.5V supply range) that must be decoupled to GND with at least a 22µF ceramic capacitor. |
| 10 | PVIN | power_in | Power input (2.7V to 5.5V supply range) that must be decoupled to GND with at least a 22µF ceramic capacitor. |
| 11 | GND | power_in | Ground pin; the center pad of the package is also used as GND and should be tied to a ground plane with vias underneath. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | DFN-10(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.7 | 5.5 | V | 3 | ||
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 3 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=VIN | 3 | |
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN=0 | 3 | |
| Quiescent Current | IQ | 150 | µA | IOUT=0, VFB=VREF ⋅ 105% | 3 | ||
| PFET RON | RDS(ON)-P | 45 | mΩ | 3 | |||
| NFET RON | RDS(ON)-N | 35 | mΩ | 3 | |||
| PFET Current Limit | ILIM | 6 | A | 3 | |||
| EN Rising Threshold | VENH | 1.5 | V | 3 | |||
| EN Falling Threshold | VENL | 0.4 | V | 3 | |||
| Input UVLO Threshold | VUVLO | 2.7 | V | 3 | |||
| UVLO Hysteresis | VHYS | 0.2 | V | 3 | |||
| Oscillator Frequency | FOSC | 1 | MHz | IOUT=1A | 3 | ||
| Min ON Time | 80 | ns | 3 | ||||
| Max Duty Cycle | 100 | % | 3 | ||||
| Thermal Shutdown Temperature | TSD | 150 | °C | Shutdown temperature | 3 | ||
| Thermal Shutdown Hysteresis | TSD | 10 | °C | Hysteresis | 3 | ||
| Soft Start Time | tSS | 6 | ms | CSS=100nF | 3 | ||
| Soft Start Time without CSS | tSS | 0.6 | ms | Without CSS | 3 | ||
| Phase Node Discharge Resistance | RDISCHG | 40 | Ω | 3 | |||
| Supply Input Voltage (absolute maximum) | -0.3 | 6.5 | V | 2 | |||
| Enable, FB Voltage (absolute maximum) | -0.3 | V | Printed as VIN + 0.6V | 2 | |||
| Power Dissipation | PD | 2.6 | W | TA = 25°C, DFN3X3-10 | 2 | ||
| Package Thermal Resistance junction-to-ambient | θJA | 38 | °C/W | 2 | |||
| Package Thermal Resistance junction-to-case | θJC | 8 | °C/W | 2 | |||
| Junction Temperature Range (absolute maximum) | -40 | 150 | °C | 2 | |||
| Lead Temperature (soldering, 10 sec) | 260 | °C | Soldering, 10 sec | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| ESD HBM | 2 | kV | Human Body Model | 2 | |||
| ESD MM | 200 | V | Machine Model | 2 | |||
| Supply Input Voltage (recommended) | 2.7 | 5.5 | V | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range (recommended) | -40 | 85 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin must | 7 |
CAD (KiCad official)
- Symbol:
SY8035DBC - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
sy8035dbc-etched.step/sy8035dbc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8035dbc.step/sy8035dbc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (9 pp, sha256
7f77345b846744a4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).