component
SY8003C1DFC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSY8003C1DFC
Silergy Corp · DC-DC Converters · DFN-8-EP(2x2)
SY8003C1DFC from Silergy Corp, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Output feedback pin; connect to the center of the output resistor divider to set VOUT = 0.6×(1+R1/R2). |
| 2 | PG | output | Open-drain power good indicator, low if the output is below 90% or above 120% of the regulation voltage and high otherwise; requires a pull-up resistor to the input. |
| 3 | IN | power_in | Power input pin; decouple to GND with at least a 10µF ceramic capacitor, with an input voltage range of 2.7V to 5.5V. |
| 4 | PGND | power_in | Power ground pin, also connected to the exposed paddle. |
| 5 | NC | unconnected | No connection. |
| 6 | LX | output | Inductor pin; connect to the switching node of the inductor. |
| 7 | EN | input | Enable control; pull high (above 1.5V) to turn on and low (below 0.4V) to shut down, and do not leave it floating. |
| 8 | SGND | power_in | Signal ground pin. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | DFN-8-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.7 | 5.5 | V | 3 | ||
| Quiescent Current | IQ | 55 | µA | IOUT=0, VFB=VREF×105% | 3 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN=0 | 3 | |
| Feedback Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | 3 | |
| PFET RON | RDS(ON),P | 110 | mΩ | 3 | |||
| NFET RON | RDS(ON),N | 80 | mΩ | 3 | |||
| PFET Current Limit | ILIM | 3.5 | A | 3 | |||
| EN Rising Threshold | VENH | 1.5 | V | 3 | |||
| EN Falling Threshold | VENL | 0.4 | V | 3 | |||
| Input UVLO Threshold | VUVLO | 2.65 | V | 3 | |||
| UVLO Hysteresis | VHYS | 0.2 | V | 3 | |||
| Oscillator Frequency | FOSC | 3 | MHz | IOUT=500mA | 3 | ||
| PG High Delay Time | 0.1 | 1 | µs | 3 | |||
| PG Rising Threshold | VFB,HV | 0.54 | V | 3 | |||
| PG Under Voltage Threshold | VFB,LV | 0.54 | V | 3 | |||
| PG Under Voltage Delay Time | 20 | us | 3 | ||||
| PG Over Voltage Threshold | VFB,OV | 0.69 | 0.72 | 0.75 | V | 3 | |
| Over Voltage Protection Threshold | VOVP | 0.69 | 0.72 | 0.75 | V | 3 | |
| Over Voltage Deglitch Timeout | tOV | 10 | 20 | 30 | µs | 3 | |
| Short Circuit Protection Delay Time | tDELAY-SC | 20 | µs | 3 | |||
| Min ON Time | 75 | ns | 3 | ||||
| Max Duty Cycle | 100 | % | 3 | ||||
| Soft-start Time | tSS | 1 | ms | 3 | |||
| Output Discharge Switch On Resistance | RDISCH | 50 | Ω | 3 | |||
| Thermal Shutdown Temperature | TSD | 150 | °C | 3 | |||
| Supply Input Voltage (LX) | VIN | 6 | V | Supply Input Voltage, LX | 3 | ||
| Enable, FB Voltage | 6 | V | 3 | ||||
| Power Dissipation | PD | 1 | W | TA = 25°C, DFN2×2-8 | 3 | ||
| Junction-to-ambient Thermal Resistance | θJA | 120 | °C/W | Note 2 | 3 | ||
| Junction-to-case Thermal Resistance | θJC | 8.2 | °C/W | 3 | |||
| Junction Temperature Range (absolute maximum) | 150 | °C | 3 | ||||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | 3 | ||||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Supply Input Voltage (recommended) | VIN | 2.7 | 5.5 | V | 3 | ||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with LX pin | 8 |
CAD (KiCad official)
- Symbol:
SY8003C1DFC - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
sy8003c1dfc-etched.step/sy8003c1dfc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8003c1dfc.step/sy8003c1dfc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (11 pp, sha256
dacf595b19d33d21, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).