component
SY7400FCC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSY7400FCC
Silergy Corp · DC-DC Converters · SOP-8-EP
SY7400FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin; the datasheet gives no function for it. |
| 2 | NC | unconnected | No connect pin; the datasheet gives no function for it. |
| 3 | LX | output | Inductor node connected between the IN pin and the LX pin; the absolute maximum rating for LX is 63V. |
| 4 | GND | power_in | Ground pin; maximizing the PCB copper area connected to GND is recommended for thermal and noise performance. |
| 5 | IN | power_in | Input pin to be decoupled to GND with a 1uF ceramic capacitor; the input voltage range is 5V to 60V with an absolute maximum of 63V. |
| 6 | OVP | input | Over voltage protection pin with a typical threshold value of 60V. |
| 7 | EN/PWM | input | Enable and dimming control pin; the EN rising threshold is 1.8V and the falling threshold is 0.4V, and a low signal turns off the internal MOSFET. |
| 8 | FB | input | Feedback pin; connect resistor R1 between FB and GND to program the output current IOUT = 0.2V/RSEN. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 5 | 60 | V | 3 | ||
| Feedback Reference Voltage | VREF | 196 | 200 | 204 | mV | 3 | |
| Absolute maximum LX, IN, EN voltage | 63 | V | LX, IN, EN pins | 2 | |||
| Absolute maximum all other pins voltage | 4 | V | All other pins | 2 | |||
| Power Dissipation | PD | 3.3 | W | TA = 25°C, SO8E | 2 | ||
| Junction Temperature Range (absolute maximum) | -40 | 150 | °C | 2 | |||
| Lead Temperature (soldering) | 260 | °C | Soldering, 10 sec. | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Input Voltage Supply (recommended) | 5 | 60 | V | 2 | |||
| All other pins (recommended) | 3.6 | V | All other pins | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range (recommended) | -40 | 85 | °C | 2 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 30 | °C/W | Note 2: natural convection, TA=25°C, JEDEC 51-3 test board | 2 | ||
| Package Thermal Resistance, junction-to-case | θJC | 10 | °C/W | 2 | |||
| Quiescent Current | IQ | 0.75 | mA | VFB=0V | 3 | ||
| Shutdown Current | ISHDN | 20 | uA | EN=0 | 3 | ||
| FB Input Current | IFB | 1 | uA | VFB=0V | 3 | ||
| Low Side Main FET RON | RDS(ON) | 650 | mΩ | 3 | |||
| Main FET Current Limit | ILIM | 1.2 | A | 3 | |||
| EN Rising Threshold | VENH | 1.8 | V | 3 | |||
| EN Falling Threshold | VENL | 0.4 | V | 3 | |||
| Input UVLO ON Threshold | VUVLO | 4.5 | V | 3 | |||
| Input UVLO OFF Threshold | VUVLO | 4.3 | V | 3 | |||
| Oscillator Frequency | FOSC | 400 | kHz | IOUT=100mA | 3 | ||
| Min On Time | 150 | ns | 3 | ||||
| Max Duty Cycle | 95 | % | 3 | ||||
| Thermal Shutdown | TSD | 150 | ℃ | 3 | |||
| Thermal Hysteresis | THYST | 20 | ℃ | 3 | |||
| OVP Rising Threshold | VOVP | 1.2 | V | 3 | |||
| OVP Rising Hysteresis | VOVP,HYS | 50 | mV | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 4) The PCB copper area associated with LX pin must be | 7 |
CAD (KiCad official)
- Symbol:
SY7400FCC - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
sy7400fcc-etched.step/sy7400fcc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy7400fcc.step/sy7400fcc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (9 pp, sha256
9688fd9b8967f25a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).