component
SY6982EQDC
Public Made by Adomby adom
Silergy Corp Battery Management ICs, QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSY6982EQDC
Silergy Corp · Battery Management ICs · QFN-16(3x3)
SY6982EQDC from Silergy Corp, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STAT | output | Open-drain charge status indication pin, pulled high to SVIN through an LED; LED on means charging, off means charge done, flashing at 1.3Hz means fault. |
| 2 | SYSRT | output | System ON/OFF control output that goes low when VBAT is below 6V to turn the system off and high when VBAT is above 6V to turn it on. |
| 3 | TIM | passive | Charge time limit pin; connect a capacitor to ground, charged by an internal current source to set the TC and CC mode time limits (TC limit about 1/9 of CC limit). |
| 4 | NTC | input | Battery thermal protection pin with UTP threshold typically 75% of VSVIN and OTP threshold typically 30% of VSVIN; pull up to SVIN to disable charging and run as a normal boost regulator, pull to ground to shut down the IC. |
| 5 | CV | input | Battery constant-voltage selection pin; below 1V selects 8.4V and above 2V selects 8.7V. |
| 6 | VSEN | input | Voltage sense of SVIN; when it drops to the internal 1.195V reference, SVIN is clamped to the set value and input current is limited. |
| 7 | EN | input | Enable control pin; high logic (above 1.5V) enables the device and low logic (below 0.4V) disables it. |
| 8 | SGND | power_in | Signal ground pin. |
| 9 | ICHG | passive | Charge current program pin; connect resistor RICHG to ground, with ICC=(1V/RICHG)x10000 and ITC=(1V/RICHG)x1000. |
| 10 | BD | passive | Drain of the internal blocking FET (bus voltage regulated at 6V in short-circuit recovery); bypass with at least 4.7uF ceramic capacitor to GND. |
| 11 | BST | passive | Boost-strap pin supplying the rectified FET gate driver; decouple to LX with a 0.1uF ceramic capacitor. |
| 12 | BAT | bidirectional | Battery positive pin. |
| 13 | BD | passive | Drain of the internal blocking FET; bypass with at least 4.7uF ceramic capacitor to GND. |
| 14 | LX | passive | Switch node pin connected to the external inductor. |
| 15 | PGND | power_in | Power ground pin. |
| 16 | SVIN | power_in | Analog power input pin (3.6V to 5.5V recommended) with OVP and UVLO; connect a MLCC to ground to decouple high harmonic noise. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | QFN-16(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| SVIN supply voltage | VSVIN | 3.6 | 16 | V | 4 | ||
| VSVIN under voltage lockout | VUVLO | 3.6 | V | VSVIN rising, measured from VSVIN to GND | 4 | ||
| UVLO hysteresis | ΔVUVLO | 100 | mV | Measured from VSVIN to GND | 4 | ||
| Input overvoltage protection | VOVP | 5.8 | V | VSVIN rising, measured from VSVIN to GND | 4 | ||
| Input OVP hysteresis | ΔVOVP | 0.5 | V | Measured from VSVIN to GND | 4 | ||
| Battery discharge current | IBAT | 10 | uA | Shutdown IC, EN=NTC=0 | 4 | ||
| Input quiescent current | IIN | 1.5 | mA | Disable Charge, EN=1, NTC=0 | 4 | ||
| Switching frequency | fSW | 1000 | kHz | 4 | |||
| RDS(ON) of Main N-FET | RNFET_M | 80 | mΩ | 4 | |||
| RDS(ON) of Rectified N-FET | RNFET_R | 40 | mΩ | 4 | |||
| RDS(ON) of Blocking N-FET | RNFET_B | 40 | mΩ | 4 | |||
| 2-Cell CV charge mode voltage (8.4V) | VCV | 8.358 | 8.4 | 8.442 | V | VCV<1V | 4 |
| 2-Cell CV charge mode voltage (8.7V) | VCV | 8.656 | 8.7 | 8.743 | V | VCV>2V | 4 |
| 2-Cell Recharge Voltage | ΔVRCH | 100 | 200 | 300 | mV | 4 | |
| 2-cell TC charge mode threshold | VTRK | 5.4 | 5.6 | 5.8 | V | Rising edge | 4 |
| CC charge current accuracy | -10 | 10 | % | ICC=1000mA | 4 | ||
| Trickle charge current accuracy | -50 | 50 | % | ITC=100mA | 4 | ||
| Termination current | ITERM | 50 | 100 | 150 | mA | ICC=1000mA | 4 |
| Output voltage OVP threshold | VOVP | 105 | 110 | 115 | %VCV | 4 | |
| Voltage reference of VSEN | VThreshold | 1.171 | 1.195 | 1.219 | V | 4 | |
| Trickle current charge timeout | TTC | 0.23 | 0.5 | 0.67 | hour | CTIM=330nF | 5 |
| Constant current charge timeout | TCC | 3 | 4.5 | 6 | hour | 5 | |
| Output short protection threshold | VSHORT | 1.7 | 2 | 2.3 | V | 5 | |
| Bus voltage regulation | VBD | 5.8 | 6 | 6.2 | V | 5 | |
| Under temperature protection | UTP | 70 | 75 | 80 | %VSVIN | Falling edge | 5 |
| Over temperature protection | OTP | 28 | 30 | 32 | %VSVIN | Rising edge | 5 |
| Enable high level | VENH | 1.5 | V | 5 | |||
| Enable low level | VENL | 0.4 | V | 5 | |||
| Thermal shutdown temperature | TSD | 160 | ºC | Rising Threshold | 5 | ||
| Pin voltage (STAT, NTC, CV, VSEN, EN, ICHG, BD, BAT, LX, SVIN) | 18 | V | 3 | ||||
| Pin voltage (SYSRT, TIM, BST-LX) | 4 | V | 3 | ||||
| LX pin current continuous | 5 | A | 3 | ||||
| Power dissipation | PD | 2.6 | W | TA=25°C, QFN3X3 | 3 | ||
| Junction temperature range | TJ | -40 | 125 | °C | 3 | ||
| Lead temperature | 260 | °C | Soldering, 10 sec | 3 | |||
| Storage temperature range | TSTG | -65 | 125 | °C | 3 | ||
| Thermal resistance junction-ambient | θJA | 38 | °C/W | 3 | |||
| Thermal resistance junction-case | θJC | 4 | °C/W | 3 | |||
| SVIN operating voltage | SVIN | 3.6 | 5.5 | V | 3 | ||
| Operating pin voltage (STAT, NTC, CV, VSEN, EN, ICHG, BD, BAT, LX) | -0.3 | 16 | V | 3 | |||
| Operating pin voltage (SYSRT, TIM) | -0.3 | 3.3 | V | 3 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 3 | ||
| Ambient temperature range | TA | -40 | 85 | °C | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) CSVIN must be close to pin SVIN and GND. 4) The PCB copper area associated with LX pin | 10 |
CAD (KiCad official)
- Symbol:
SY6982EQDC - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
sy6982eqdc-etched.step/sy6982eqdc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy6982eqdc.step/sy6982eqdc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (12 pp, sha256
7088f0c350868aba, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).