# SY6935QDC

**Silergy Corp** · Battery Management ICs · QFN-16(3x3)

SY6935QDC from Silergy Corp, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RS | input | Charge current sense resistor positive pin; the voltage drop between RS and BAT is used for charge current regulation and charge termination detection (RS limited to BAT±0.25V recommended). |
| 2 | CELL | input | Battery voltage selection pin: floating for two-cell battery and grounded for single-cell battery; must not be pulled higher than 3.3V. |
| 3 | TIM | passive | Charge time-out programming pin; connect a capacitor to ground to set the time-out threshold for trickle and fast charge modes (TC limit is about 1/9 of fast charge time). |
| 4 | NTC | input | Battery thermal sense pin with UTP threshold typically 75% VIN and OTP threshold typically 45% VIN; pulling it low for more than 100ms refreshes the adaptive input power limit threshold. |
| 5 | CV | input | Battery CV voltage selection pin (below 0.4V selects 4.2V/cell, above 1.5V selects 4.35V/cell). |
| 6 | VSEN | input | Input voltage sense pin for adaptive input power limit; when the voltage drops to the internal 1.19V reference, VIN is clamped and input current is limited. |
| 7 | EN | input | Enable control pin: high logic (above 1.5V) enables, low logic (below 0.4V) disables. |
| 8 | SGND | power_in | Signal ground pin. |
| 9 | STAT | output | Open-drain charge status indication pin; pulled high to IN through a LED, which is on during charging, off when done, and flashing at 1.3Hz in fault mode. |
| 10 | BD | passive | Connects to the drain of the internal blocking FET; bypass with at least 10uF ceramic capacitor to GND. |
| 11 | BST | passive | Boot-strap pin supplying the main FET gate driver; decouple to LX with a 0.1uF ceramic capacitor. |
| 12 | IN | power_in | DC power input pin (4V to 14V operating) with OVP and UVLO functions; connect an MLCC to ground to decouple high-frequency noise. |
| 13 | BD | passive | Connects to the drain of the internal blocking FET; bypass with at least 10uF ceramic capacitor to GND. |
| 14 | LX | passive | Switch node pin; connect to the external inductor. |
| 15 | PGND | power_in | Power ground pin. |
| 16 | BAT | input | Battery voltage sense pin. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | QFN-16(3x3) |
| Category | Power Management ICs |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage operation range | VIN | 4 |  | 14 | V |  | 4 |
| Input overvoltage protection | VIN_OVP |  | 13.5 |  | V | VIN rising and measured from IN to ground | 4 |
| Battery discharge current | IBAT |  | 5 | 10 | uA | VIN absent or EN=Low | 4 |
| Input quiescent current | IIN |  | 0.8 | 1.1 | mA | Disable Charge | 4 |
| Battery charge voltage 1-cell 4.2V | VBAT | 4.179 | 4.2 | 4.221 | V | 1-cell battery, Vcv<0.4V | 4 |
| Battery charge voltage 1-cell 4.35V | VBAT | 4.328 | 4.35 | 4.371 | V | 1-cell battery, Vcv>1.5V | 4 |
| Battery charge voltage 2-cell 8.4V | VBAT | 8.358 | 8.4 | 8.442 | V | 2-cell battery, Vcv<0.4V | 4 |
| Battery charge voltage 2-cell 8.7V | VBAT | 8.656 | 8.7 | 8.744 | V | 2-cell battery, Vcv>1.5V | 4 |
| Recharge threshold 1-cell | ΔVRCH | 50 | 100 | 150 | mV | 1-cell battery | 4 |
| Recharge threshold 2-cell | ΔVRCH | 100 | 200 | 300 | mV | 2-cell battery | 4 |
| Trickle charge rising edge threshold 1-cell | VTRK | 2.7 | 2.8 | 2.9 | V | 1-cell battery | 4 |
| Trickle charge rising edge threshold 2-cell | VTRK | 5.4 | 5.6 | 5.8 | V | 2-cell battery | 4 |
| Charge current accuracy CC mode | ICC | -10 |  | 10 | % | ICC=25mV/RS | 4 |
| Charge current accuracy trickle mode | ITC | -50 |  | 50 | % | ITC=2.5mV/RS | 4 |
| Termination current accuracy | ITERM | -50 |  | 50 | % | ITERM=2.5mV/RS | 4 |
| Output voltage OVP threshold | VO_OVP | 105 | 110 | 115 | % VCV |  | 4 |
| Reference for adaptive input power limit | VSEN | 1.16 | 1.19 | 1.22 | V |  | 4 |
| Trickle current charge timeout | TTC | 0.36 | 0.5 | 0.64 | hour |  | 4 |
| Constant current charge timeout | TCC | 3.5 | 4.5 | 5.5 | hour |  | 4 |
| Output short protection threshold, falling edge | VSHORT | 1.7 | 2 | 2.3 | V |  | 5 |
| Auto shutdown voltage threshold | ΔVASD | 40 | 90 | 140 | mV | VIN fall, Measured from IN to VBAT | 5 |
| Under temperature protection | UTP | 70 | 75 | 80 | % VIN |  | 5 |
| Over temperature protection | OTP | 43 | 45 | 47 | % VIN |  | 5 |
| High level logic for enable control | VEN | 1.5 |  |  | V |  | 5 |
| Low level logic for enable control | VEN |  |  | 0.4 | V |  | 5 |
| CV high level logic | VCV | 1.5 |  |  | V |  | 5 |
| CV low level logic | VCV |  |  | 0.4 | V |  | 5 |
| Input voltage lockout threshold | VUVLO |  | 4 |  | V | VIN rising and measured from IN to ground | 4 |
| Switching frequency | fSW |  | 500 |  | kHz |  | 4 |
| RDS(ON) of Main N-FET | RNFET_M |  | 25 |  | mΩ |  | 4 |
| RDS(ON) of Rectified N-FET | RNFET_R |  | 45 |  | mΩ |  | 4 |
| RDS(ON) of Blocking N-FET | RNFET_B |  | 35 |  | mΩ |  | 4 |
| Thermal fold-back threshold | TFold |  | 120 |  | ºC |  | 5 |
| Thermal shutdown temperature | TSD |  | 160 |  | ºC | Rising Threshold | 5 |
| Abs max IN, BAT, LX, NTC, STAT, BD, EN, CV, VSEN |  |  |  | 18 | V |  | 3 |
| Abs max TIM, CELL |  |  |  | 4 | V |  | 3 |
| Abs max BST-LX voltage |  |  |  | 4 | V |  | 3 |
| Abs max LX pin current continuous |  |  |  | 5 | A |  | 3 |
| Power dissipation | PD |  |  | 2.1 | W | TA = 25°C, QFN3x3 | 3 |
| Junction temperature range (abs max) | TJ | -40 |  | 125 | °C |  | 3 |
| Lead temperature |  |  |  | 260 | °C | Soldering, 10 sec. | 3 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 3 |
| Thermal resistance junction to ambient | θJA |  | 48 |  | °C/W |  | 3 |
| Thermal resistance junction to case | θJC |  | 4 |  | °C/W |  | 3 |
| Recommended IN voltage | IN | 4 |  | 14 | V |  | 3 |
| Recommended BAT, LX, NTC, STAT, BD, EN, CV, VSEN |  | 0 |  | 16 | V |  | 3 |
| Recommended TIM, CELL |  | 0 |  | 3.3 | V |  | 3 |
| Recommended BST-LX voltage |  | 0 |  | 3.3 | V |  | 3 |
| Recommended LX pin current continuous |  |  |  | 4.5 | A |  | 3 |
| Recommended junction temperature range | TJ | -40 |  | 100 | °C |  | 3 |
| Recommended ambient temperature range | TA | -40 |  | 85 | °C |  | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | 4) The PCB copper area associated with LX pin | 12 |

## CAD (KiCad official)

- Symbol: `SY6935QDC`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `sy6935qdc-etched.step` / `sy6935qdc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy6935qdc.step` / `sy6935qdc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Silergy Corp datasheet](docs/sy6935qdc-datasheet.pdf) (15 pp, sha256 `a3eb13df3fdd227f`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sy6935qdc-datasheet.pdf)