component

SY59103NFCC

Public Made by Adom

by adom

Silergy Corp AC-DC Controllers And Regulators, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)sy59103nfccfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers sy59103nfcc: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
sy59103nfcc-etched.glb Publish 0.1.0 · Ray 17d ago
sy59103nfcc-etched.step sy59103nfcc: factory component page (tier=lcsc) · Ray 17d ago
sy59103nfcc-hero.glb sy59103nfcc: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
sy59103nfcc-hero.overlay.json Publish 0.1.0 · Ray 17d ago
sy59103nfcc.glb Publish 0.1.0 · Ray 17d ago
sy59103nfcc.kicad_mod Publish 0.1.0 · Ray 17d ago
sy59103nfcc.kicad_sym Publish 0.1.0 · Ray 17d ago
sy59103nfcc.lbr Publish 0.1.0 · Ray 17d ago
sy59103nfcc.step Publish 0.1.0 · Ray 17d ago

SY59103NFCC

Silergy Corp · AC-DC Controllers And Regulators · SOP-8-EP

SY59103NFCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CF2 input TRIAC or non-TRIAC mode detection input; a 1µF to 2.2µF capacitor is recommended, usually with a resistor in parallel to GND, and the absolute maximum rating is -0.3V to 3.6V.
2 BUS1 passive Internal compensation pin that requires a 2.2nF capacitor to GND; the absolute maximum rating is -0.3V to 25V.
3 IBLD passive Bleeding current pin that draws current from BUS to achieve good dimmer compatibility; the absolute maximum rating is -0.3V to 600V.
4 PVIN passive Drain of the integrated power MOSFET; the absolute maximum rating is -0.3V to 350V, and the MOSFET BV is 350V minimum.
5 VIN power_in IC power supply pin with a recommended operating range of 12V to 18V, an absolute maximum rating of -0.3V to 21V, and a supply current limit of 10mA.
6 VS power_in Source of the integrated power MOSFET used to sense output current; the absolute maximum rating is -0.3V to 3.6V.
7 CF input TRIAC angle detection input; the absolute maximum rating is -0.3V to 3.6V.
8 COMP passive Loop compensation pin where a 68nF to 100nF capacitor is suggested; the absolute maximum rating is -0.3V to 25V.
9 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOP-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN Turn-on Threshold VVIN_ON 15 17.5 20 V 4
VIN Turn-off Threshold VVIN_OFF 9.5 11.5 13.5 V 4
Quiescent Current IQ 210 255 320 µA 4
Internal Reference Voltage VREF 275 284 293 mV 4
PVIN pin voltage PVIN -0.3 350 V 3
IBLD pin voltage IBLD -0.3 600 V 3
COMP, BUS1 pin voltage COMP, BUS1 -0.3 25 V 3
CF, CF2, VS pin voltage CF, CF2, VS -0.3 3.6 V 3
VIN pin voltage VIN -0.3 21 V 3
Supply current IVIN 10 mA 3
Power Dissipation SO8E 3.3 W @ TA = 25°C 3
VIN recommended operating voltage VIN 12 18 V 3
Temperature Range -40 150 °C 3
Storage Temperature Range -65 150 °C 3
Lead Temperature (Soldering) 260 °C Soldering, 10 sec. 3
Thermal Resistance, junction-to-ambient SO8E θJA 30 °C/W Note 2: natural convection, TA = 25°C, JEDEC 51-3 test board 3
Thermal Resistance, junction-to-case SO8E θJC 10 °C/W SO8E 3
BV of Integrated MOSFET VDrain 350 V 4
Thermal Fold Back Temperature TFB 150 ℃ 4
Thermal Shutdown Temperature TSD 160 ℃ 4

CAD (KiCad official)

  • Symbol: SY59103NFCC
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: sy59103nfcc-etched.step / sy59103nfcc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy59103nfcc.step / sy59103nfcc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (9 pp, sha256 2b01ee2589f2e655, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF