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SY100ELT22LZG

Public Made by Adom

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Microchip Tech Translators / Level Shifters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssy100elt22lzgfactory-2.0.0extractor-text

Verified SY100ELT22LZG

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SY100ELT22LZG · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C637613, digikey 576-3389-5-ND, mouser 998-SY100ELT22LZG
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-vkmn_sc6/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sy100elt22lzg.kicad_sym✓ sy100elt22lzg.kicad_mod✓ sy100elt22lzg.step
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Ray Publish 0.1.0 9588459 16h ago

SY100ELT22LZG

Microchip Tech · Translators / Level Shifters · SOIC-8

SY100ELT22LZG from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q0 output Non-inverting differential LVPECL output for channel 0, VOH 2220 to 2420 mV at VCC = 3.3V, TA = -40°C.
2 /Q0 output Inverting differential LVPECL output for channel 0, VOL 1470 to 1750 mV at VCC = 3.3V, TA = -40°C.
3 Q1 output Non-inverting differential LVPECL output for channel 1, with within-device skew of max 100 ps.
4 /Q1 output Inverting differential LVPECL output for channel 1, with within-device skew of max 100 ps.
5 GND power_in Ground; only +3.3V and ground are required because LVPECL levels are used.
6 D1 input LVTTL input for channel 1 (VIH min 2.0V, VIL max 0.8V, absolute max -0.5V to VCC).
7 D0 input LVTTL input for channel 0 (VIH min 2.0V, VIL max 0.8V, absolute max -0.5V to VCC).
8 VCC power_in +3.3V supply, operating range 3.0V to 3.8V, absolute maximum -0.5V to +7.0V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Logic ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 7 V 2
LVTTL Input Voltage VIN -0.5 V -0.5V to VCC 2
LVTTL Input Current IIN -30 5 mA 2
LVPECL Output Current (Continuous) 50 mA Continuous 2
LVPECL Output Current (Surge) 100 mA Surge 2
Power Supply Current ICC 25 mA 2
Input High Voltage VIH 2 V 2
Input Low Voltage VIL 0.8 V 2
Input High Current IIH 20 µA VIN = 2.7V 2
Input High Current IIH 100 µA VIN = VCC 2
Input Low Current IIL -0.2 mA VIN = 0.5V 2
Input Clamp Voltage VIK -1.2 V IIN = -18 mA 2
Output High Voltage VOH 2220 2420 mV TA = -40°C, Note 1. 2
Output High Voltage VOH 2275 2420 mV TA = 0°C to +85°C, Note 1. 2
Output Low Voltage VOL 1470 1750 mV TA = -40°C, Note 1. 2
Output Low Voltage VOL 1490 1680 mV TA = 0°C to +85°C, Note 1. 2
Propagation Delay to Output tPD 100 600 ps 50Ω to VCC, 2.0V 3
Output Rise/Fall Time, 20% to 80% tr/tf 200 500 ps 50Ω to VCC, 2.0V 3
Part-to-Part Skew tSKPP 500 ps 50Ω to VCC, 2.0V 3
Within-Device Skew tSKEW 100 ps 50Ω to VCC, 2.0V 3
Operating Temperature Range TA -40 85 °C 4
Storage Temperature Range TS -65 150 °C 4
Lead Temperature 260 °C Soldering, 20s 4
Supply Voltage (operating) VCC 3 3.8 V Electrical characteristics test range 2

CAD (KiCad official)

  • Symbol: SY100ELT22LZG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sy100elt22lzg-etched.step / sy100elt22lzg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy100elt22lzg.step / sy100elt22lzg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (14 pp, sha256 8e8feec2eff86f85, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF