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SVF20NE50PN

Public Made by Adom

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Hangzhou Silan Microelectronics MOSFETs, TO-3P-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SVF20NE50PN

Hangzhou Silan Microelectronics · MOSFETs · TO-3P-3

SVF20NE50PN from Hangzhou Silan Microelectronics, in a TO-3P-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal of the N-channel MOSFET, with a maximum gate-source voltage of ±30 V and a threshold of 2.0 to 4.0 V.
2 Drain passive Drain terminal of the MOSFET, rated for 500 V drain-source voltage and 20 A continuous drain current at TC=25°C.
3 Source passive Source terminal of the MOSFET, with a continuous source (body diode) current of 20.0 A and a pulsed source current of 80.0 A.

Key specifications

Parameter Value
Manufacturer Hangzhou Silan Microelectronics
Package TO-3P-3
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 500 V VGS=0V, ID=250µA 2
Drain-Source Leakage Current IDSS 1 µA VDS=500V, VGS=0V 2
Gate-Source Leakage Current IGSS -100 100 µA VGS=±25V, VDS=0V 2
Gate Threshold Voltage VGS(th) 2 4 V VGS=VDS, ID=250µA 2
On State Resistance RDS(on) 0.18 0.27 Ω VGS=10V, ID=10.0A 2
Source Current IS 20 A Integral reverse P-N junction diode in the MOSFET 3
Pulsed Source Current ISM 80 A Integral reverse P-N junction diode in the MOSFET 3
Diode Forward Voltage VSD 1.3 V IS=20.0A, VGS=0V 3
Drain-Source Voltage VDS 500 V TC=25C 2
Gate-Source Voltage VGS -30 30 V TC=25C 2
Drain Current ID 20 A TC=25°C 2
Drain Current ID 12.6 A TC=100°C 2
Drain Current Pulsed IDM 80 A TC=25C 2
Power Dissipation PD 252 W TC=25C 2
Power Dissipation Derating PD 2.02 W/C Derate above 25C 2
Single Pulsed Avalanche Energy EAS 2812 mJ L=30mH, IAS=11.60A, VDD=165V, RG=25, starting TJ=25C 2
Operation Junction Temperature Range TJ -55 150 C 2
Storage Temperature Range Tstg -55 150 C 2
Thermal Resistance, Junction-to-Case RθJC 0.5 C/W 2
Thermal Resistance, Junction-to-Ambient RθJA 50 C/W 2
Input Capacitance Ciss 3504 pF VDS=25V, VGS=0V, f=1.0MHZ 2
Output Capacitance Coss 425 pF VDS=25V, VGS=0V, f=1.0MHZ 2
Reverse Transfer Capacitance Crss 12.03 pF VDS=25V, VGS=0V, f=1.0MHZ 2
Turn-on Delay Time td(on) 80.67 ns VDD=250V, RG=25, ID=20.0A 2
Turn-on Rise Time tr 150.67 ns VDD=250V, RG=25, ID=20.0A 2
Turn-off Delay Time td(off) 198.67 ns VDD=250V, RG=25, ID=20.0A 2
Turn-off Fall Time tf 112 ns VDD=250V, RG=25, ID=20.0A 2
Total Gate Charge Qg 58.38 nC VDD=400V, VGS=10V, ID=20.0A 2
Gate-Source Charge Qgs 16.89 nC VDD=400V, VGS=10V, ID=20.0A 2
Gate-Drain Charge Qgd 18.33 nC VDD=400V, VGS=10V, ID=20.0A 2
Reverse Recovery Time Trr 577.53 ns IS=20.0A, VGS=0V, dIF/dt=100A/µS 3
Reverse Recovery Charge Qrr 7.78 µC IS=20.0A, VGS=0V, dIF/dt=100A/µS 3

CAD (KiCad official)

  • Symbol: SVF20NE50PN
  • Footprint: Package_TO_SOT_THT:TO-3P-3_Vertical
  • 3D model: TO-3P-3 (KiCad packages3D, STEP)
  • 3D model files: svf20ne50pn-etched.step / svf20ne50pn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); svf20ne50pn.step / svf20ne50pn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Hangzhou Silan Microelectronics datasheet (7 pp, sha256 e72337b9d453de24, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF