main
Ray Publish 0.1.0 2f494dd 17d ago

SUM70101EL-GE3

Vishay Intertech · MOSFETs · TO-263

SUM70101EL-GE3 from Vishay Intertech, in a TO-263. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; logic-level drive with RDS(on) max 0.0150 ohm specified at VGS = -4.5 V and 0.0101 ohm at -10 V, absolute maximum VGS ±20 V.
2 D passive Drain (middle lead, connected to the heat-sink tab); VDS rated -100 V, continuous ID -120 A at TC = 25 °C, pulsed IDM -240 A.
3 S passive Source; body-diode continuous current IS -110 A and pulsed ISM -240 A.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TO-263
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS -100 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID -120 A TJ = 175 °C, TC = 25 °C 1
Continuous drain current ID -78 A TJ = 175 °C, TC = 125 °C 1
Pulsed drain current (100 μs) IDM -240 A 100 μs pulse 1
Avalanche current IAS -75 A L = 0.1 mH 1
Single pulse avalanche energy EAS 281 mJ 1
Power dissipation PD 375 W TC = 25 °C 1
Power dissipation PD 125 W TC = 125 °C 1
Operating junction and storage temperature range TJ, Tstg -55 175 °C 1
Drain-source breakdown voltage VDS -100 V VGS = 0 V, ID = -250 μA 2
Gate threshold voltage VGS(th) -1.5 -2.5 V VDS = VGS, ID = -250 μA 2
Gate-body leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero gate voltage drain current IDSS -1 μA VDS = -100 V, VGS = 0 V 2
Zero gate voltage drain current IDSS -50 μA VDS = -100 V, VGS = 0 V, TJ = 125 °C 2
Zero gate voltage drain current IDSS -250 μA VDS = -100 V, VGS = 0 V, TJ = 175 °C 2
On-state drain current ID(on) -120 A VDS -5 V, VGS = -10 V 2
Drain-source on-state resistance RDS(on) 0.0081 0.0101 Ω VGS = -10 V, ID = -30 A 2
Drain-source on-state resistance RDS(on) 0.0114 0.015 Ω VGS = -4.5 V, ID = -20 A 2
Total gate charge Qg 125 190 nC VDS = -50 V, VGS = -10 V, ID = -110 A 2
Gate resistance Rg 1.3 6.5 13 Ω f = 1 MHz 2
Turn-on delay time td(on) 20 30 ns VDD = -50 V, RL = 0.71 Ω, ID -70 A, VGEN = -10 V, Rg = 1 Ω 2
Rise time tr 40 60 ns VDD = -50 V, RL = 0.71 Ω, ID -70 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 110 200 ns VDD = -50 V, RL = 0.71 Ω, ID -70 A, VGEN = -10 V, Rg = 1 Ω 2
Fall time tf 40 60 ns VDD = -50 V, RL = 0.71 Ω, ID -70 A, VGEN = -10 V, Rg = 1 Ω 2
Continuous current (body diode) IS -110 A TC = 25 °C 2
Pulsed current (body diode) ISM -240 A 2
Forward voltage VSD -1 -1.5 V IF = -85 A, VGS = 0 V 2
Reverse recovery time trr 110 170 ns IF = -85 A, dI/dt = 100 A/μs 2
Peak reverse recovery current IRM(REC) -7 -11 A IF = -85 A, dI/dt = 100 A/μs 2
Reverse recovery charge Qrr 0.38 0.57 μC IF = -85 A, dI/dt = 100 A/μs 2
Junction-to-ambient thermal resistance (PCB mount) RthJA 40 °C/W PCB mount 1
Junction-to-case thermal resistance RthJC 0.4 °C/W 1

CAD (KiCad official)

  • Symbol: SUM70101EL-GE3
  • Footprint: Package_TO_SOT_SMD:TO-263-2
  • 3D model: TO-263 (KiCad packages3D, STEP)
  • 3D model files: sum70101el-ge3-etched.step / sum70101el-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sum70101el-ge3.step / sum70101el-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 89ffd7a4f65c892a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF