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SUD50P10-43L-E3

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Vishay Intertech MOSFETs, TO-252. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SUD50P10-43L-E3

Vishay Intertech · MOSFETs · TO-252

SUD50P10-43L-E3 from Vishay Intertech, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the P-channel MOSFET; gate-source voltage is rated at ±20 V (VGS).
2 D passive Drain, electrically connected to the tab; drain-source voltage is -100 V (VDS) and continuous drain current is -37.1 A at TC = 25 °C.
3 S passive Source of the P-channel MOSFET; continuous source current (diode conduction) is -50 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TO-252
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -100 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID -37.1 A TJ = 175 °C, TC = 25 °C 1
Continuous Drain Current ID -31 A TJ = 175 °C, TC = 125 °C 1
Continuous Drain Current ID -9.2 A TJ = 175 °C, TA = 25 °C 1
Continuous Drain Current ID -7.7 A TJ = 175 °C, TA = 125 °C 1
Pulsed Drain Current IDM -40 A 1
Continuous Source Current (Diode Conduction) IS -50 A TC = 25 °C 1
Continuous Source Current (Diode Conduction) IS -6.9 A TA = 25 °C 1
Avalanche Current IAS -35 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 61 mJ 1
Maximum Power Dissipation PD 136 W TC = 25 °C 1
Maximum Power Dissipation PD 95 W TC = 70 °C 1
Maximum Power Dissipation PD 8.3 W TA = 25 °C 1
Maximum Power Dissipation PD 5.8 W TA = 70 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 175 °C 1
Junction-to-Ambient Thermal Resistance RthJA 15 18 °C/W t ≤ 10 s 1
Junction-to-Ambient Thermal Resistance RthJA 40 50 °C/W Steady State 1
Junction-to-Case (Drain) Thermal Resistance RthJC 0.85 1.1 °C/W 1
Drain-Source Breakdown Voltage VDS -100 V VGS = 0 V, ID = -250 µA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ±20 V 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS = -100 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS -10 µA VDS = -100 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) -40 A VDS ≥ 5 V, VGS = -10 V 2
Drain-Source On-State Resistance RDS(on) 0.036 0.043 Ω VGS = -10 V, ID = -9.2 A 2
Drain-Source On-State Resistance RDS(on) 0.04 0.048 Ω VGS = -4.5 V, ID = -7.7 A 2
Gate-Source Threshold Voltage VGS(th) -1 -3 V VDS = VGS, ID = -250 µA 2
Total Gate Charge Qg 106 160 nC VDS = -50 V, VGS = -10 V, ID = -9.2 A 2
Total Gate Charge Qg 54 81 nC VDS = -50 V, VGS = -4.5 V, ID = -9.2 A 2
Turn-On Delay Time td(on) 15 25 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -10 V, Rg = 1 Ω 2
Rise Time tr 20 30 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 110 165 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -10 V, Rg = 1 Ω 2
Fall Time tf 100 150 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-On Delay Time td(on) 42 65 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise Time tr 160 240 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -4.5 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 100 150 ns VDD = -50 V, RL = 6.5 Ω, ID ≅ -7.7 A, VGEN = -4.5 V, Rg = 1 Ω 2
Continuous Source-Drain Diode Current IS -50 A TC = 25 °C 2
Pulse Diode Forward Current ISM -40 A 2
Body Diode Voltage VSD -0.8 -1.2 V IS = -7.7 A 2
Body Diode Reverse Recovery Time trr 60 90 ns IF = -7.7 A, dI/dt = 100 A/µs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 150 225 nC IF = -7.7 A, dI/dt = 100 A/µs, TJ = 25 °C 2
VDS Temperature Coefficient ΔVDS/TJ -109 mV/°C ID = -250 µA 2
VGS(th) Temperature Coefficient ΔVGS(th)/TJ 5.9 mV/°C 2
Forward Transconductance gfs 38 S VDS = -15 V, ID = -9.2 A 2
Input Capacitance Ciss 4600 pF VDS = -50 V, VGS = 0 V, f = 1 MHz 2
Output Capacitance Coss 230 pF VDS = -50 V, VGS = 0 V, f = 1 MHz 2
Reverse Transfer Capacitance Crss 175 pF VDS = -50 V, VGS = 0 V, f = 1 MHz 2
Gate-Source Charge Qgs 14 nC VDS = -50 V, VGS = -4.5 V, ID = -9.2 A 2
Gate-Drain Charge Qgd 26 nC VDS = -50 V, VGS = -4.5 V, ID = -9.2 A 2
Gate Resistance Rg 4 Ω f = 1 MHz 2
Reverse Recovery Fall Time ta 46 ns 2
Reverse Recovery Rise Time tb 14 ns 2

CAD (KiCad official)

  • Symbol: SUD50P10-43L-E3
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: sud50p10-43l-e3-etched.step / sud50p10-43l-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sud50p10-43l-e3.step / sud50p10-43l-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (10 pp, sha256 6b9814a5b41c0e49, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF