SUD50P10-43L-E3-VB from VBsemi Elec, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	G	input	Gate terminal of the P-channel MOSFET; gate-source voltage limit is ±20 V with threshold of -1.0 to -2.5 V.
2	D	passive	Drain terminal, connected to the tab; rated for VDS of -100 V and continuous drain current of -40 A at TC = 25 °C.
3	S	passive	Source terminal of the P-channel MOSFET; continuous source current (diode conduction) is -50 A.

Key specifications

Parameter	Value
Manufacturer	VBsemi Elec
Package	TO-252
Category	Transistors/Thyristors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Drain-Source Voltage	VDS			-100	V	TC = 25 °C	1
Gate-Source Voltage	VGS	-20		20	V	TC = 25 °C	1
Continuous Drain Current	ID			-40	A	TC = 25 °C	1
Continuous Drain Current	ID			-22	A	TC = 125 °C	1
Continuous Source Current (Diode Conduction)	IS			-50	A		1
Pulsed Drain Current	IDM			-150	A		1
Single Pulse Avalanche Current	IAS			-44	A	L = 0.1 mH	1
Single Pulse Avalanche Energy	EAS			96	mJ	L = 0.1 mH	1
Maximum Power Dissipation	PD			45	W	TC = 125 °C	1
Operating Junction and Storage Temperature Range	TJ, Tstg	-55		175	°C		1
Junction-to-Ambient Thermal Resistance	RthJA			50	°C/W	PCB mount, 1" square PCB (FR-4)	1
Junction-to-Case (Drain) Thermal Resistance	RthJC			1.1	°C/W		1
Drain-Source Breakdown Voltage	VDS	-100			V	VGS = 0 V, ID = - 250 μA	2
Gate-Source Threshold Voltage	VGS(th)	-1		-2.5	V	VDS = VGS, ID = - 250 μA	2
Gate-Source Leakage	IGSS	-100		100	nA	VDS = 0 V, VGS = ± 20 V	2
Zero Gate Voltage Drain Current	IDSS			-1	μA	VGS = 0 V, VDS = - 100 V	2
Zero Gate Voltage Drain Current	IDSS			-50	μA	VGS = 0 V, VDS = - 100 V, TJ = 125 °C	2
Zero Gate Voltage Drain Current	IDSS			-250	μA	VGS = 0 V, VDS = - 100 V, TJ = 175 °C	2
On-State Drain Current	ID(on)	-30			A	VGS = - 10 V, VDS = - 5 V	2
Total Gate Charge	Qg		96	144	nC	VGS = - 10 V, VDS = - 50V, ID = - 9.2 A	2
Gate Resistance	Rg	1.5	3.13	4.7	Ω	f = 1 MHz	2
Rise Time	tr		11	17	ns	VDD = - 50 V, RL = 6.49 Ω, ID ≅ - 7.7 A, VGEN = - 10 V, Rg = 1.0 Ω	2
Turn-Off Delay Time	td(off)		78	117	ns	VDD = - 50 V, RL = 6.49 Ω, ID ≅ - 7.7 A, VGEN = - 10 V, Rg = 1.0 Ω	2
Fall Time	tf		15	23	ns	VDD = - 50 V, RL = 6.49 Ω, ID ≅ - 7.7 A, VGEN = - 10 V, Rg = 1.0 Ω	2
Pulsed Source Current	ISM			-150	A		2
Diode Forward Voltage	VSD		-0.8	-1.5	V	IF = - 7.7 A, VGS = 0 V	2
Drain-Source On-State Resistance	RDS(on)		0.033		Ω	VGS = - 10 V, ID = - 9.2 A	2
Drain-Source On-State Resistance	RDS(on)		0.037		Ω	VGS = - 4.5 V, ID = - 7.7 A	2
Forward Transconductance	gfs		35		S	VDS = - 15 V, ID = - 9.2 A	2
Input Capacitance	Ciss		4433		pF	VGS = 0 V, VDS = - 25 V, f = 1 MHz	2
Output Capacitance	Coss		301		pF	VGS = 0 V, VDS = - 25 V, f = 1 MHz	2
Reverse Transfer Capacitance	Crss		208		pF	VGS = 0 V, VDS = - 25 V, f = 1 MHz	2

CAD (KiCad official)

Symbol: SUD50P10-43L-E3-VB
Footprint: Package_TO_SOT_SMD:TO-252-2
3D model: TO-252 (KiCad packages3D, STEP)
3D model files: sud50p10-43l-e3-vb-etched.step / sud50p10-43l-e3-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sud50p10-43l-e3-vb.step / sud50p10-43l-e3-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: VBsemi Elec datasheet (9 pp, sha256 8e26aa228d417f5b, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SUD50P10-43L-E3-VB

Verified SUD50P10-43L-E3-VB

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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