STWD100YNPWY3F from STMicroelectronics, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	WDO	output	Active-low watchdog output, asserted when WDI is not toggled within tWD; configurable as open drain (needs an external pull-up to up to 6 V) or push-pull.
2	GND	power_in	Ground reference pin.
3	EN	input	Chip enable input with an internal pull-down (32 kΩ to 100 kΩ); the device is enabled when left floating, and pulses of at least 1 µs are detected while glitches under 100 ns are ignored.
4	WDI	input	Watchdog input that must be toggled within the watchdog timeout period tWD; pulses of at least 1 µs are detected and glitches shorter than 100 ns are ignored.
5	VCC	power_in	Supply voltage, specified from 2.7 V to 5.5 V with absolute maximum rating of -0.3 V to 7.0 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOT-23-5
Category	Power Management (PMIC)
Pins	5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating voltage	VCC	2.7	5	5.5	V		12
VCC supply current	ICC		13	26	µA		12
Open drain output leakage current	ILO	-1		1	µA	From output to GND or VCC	12
Input leakage current (WDI)		-1		1	µA		12
Input high voltage (WDI, EN)	VIH	0.7			V	Multiplied by VCC	12
Input low voltage (WDI, EN)	VIL			0.3	V	Multiplied by VCC	12
Output low voltage (WDO)	VOL			0.3	V	VCC ≥ 2.7 V, ISINK = 1.2 mA	12
Output low voltage (WDO)	VOL			0.4	V	VCC ≥ 4.5 V, ISINK = 3.2 mA	12
Output high voltage (WDO), push-pull only	VOH	0.8			V	VCC ≥ 2.7 V, ISOURCE = 500 µA; multiplied by VCC	12
EN pull-down resistance		32	63	100	kΩ		12
EN glitch rejection				100	ns	Glitches shorter than this are ignored	12
EN input pulse width		1			µs	Pulses of at least this duration are detected	12
Timer startup voltage	VSTART	1.9	2.2	2.7	V		13
Watchdog timeout period (STWD100xP)	tWD	2.3	3.4	4.6	ms	STWD100xP	13
WDI pulse width		1			µs	Pulses of at least this duration are detected	13
WDI glitch rejection				100	ns	Glitches shorter than this are ignored	13
Storage temperature (VCC off)	TSTG	-55		150	°C		11
Lead solder temperature for 10 seconds	TSLD			260	°C	Reflow peak 260 °C; total budget not to exceed 245 °C for more than 30 s	11
Input or output voltage	VIO	-0.3			V	Referenced to VCC + 0.3 V	11
Supply voltage	VCC	-0.3		7	V		11
Output current	IO			20	mA		11
Power dissipation	PD			320	mW		11
Supply voltage	VCC	2.7		5.5	V		12
Ambient operating temperature	TA	-40		125	°C		12

CAD (KiCad official)

Symbol: STWD100YNPWY3F
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)
3D model files: stwd100ynpwy3f-etched.step / stwd100ynpwy3f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stwd100ynpwy3f.step / stwd100ynpwy3f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (20 pp, sha256 2ec54876f17739de, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STWD100YNPWY3F

Verified STWD100YNPWY3F

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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