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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STSPIN820

STMicroelectronics · Stepper Motor Driver · QFN-24-EP(4x4)

STSPIN820 from STMicroelectronics, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	REF	input	Reference voltage for the PWM current control circuitry; operating range 0.1 to 1 V, absolute maximum −0.3 to 2 V.
2	GND	power_in	Device ground; one of two dedicated ground pins on the logic side of the package.
3	GND	power_in	Device ground; one of two dedicated ground pins on the logic side of the package.
4	SNSA	input	Full-bridge A current-regulator sense input; voltage here is compared to the internal PWM reference; operating range −1 to +1 V, absolute maximum ±2 V.
5	SENSEA1	power_out	Bridge A power-stage sense output (A1 side); connects to external shunt resistor for phase-current sensing; rated 1.5 Arms continuous.
6	SENSEA2	power_out	Bridge A power-stage sense output (A2 side); connects to external shunt resistor for phase-current sensing; rated 1.5 Arms continuous.
7	OUTA1	power_out	Full-bridge A power output, side A1; motor coil A terminal; 7-45 V operating supply range, 1.5 Arms continuous, RDSon HS+LS = 1 Ω typical.
8	OUTA2	power_out	Full-bridge A power output, side A2; motor coil A terminal; 7-45 V operating supply range, 1.5 Arms continuous, RDSon HS+LS = 1 Ω typical.
9	VS	power_in	Device supply voltage; both VS pins must be held at the same potential; operating range 7 to 45 V, absolute maximum −0.3 to 48 V.
10	VS	power_in	Device supply voltage; both VS pins must be held at the same potential; operating range 7 to 45 V, absolute maximum −0.3 to 48 V.
11	OUTB2	power_out	Full-bridge B power output, side B2; motor coil B terminal; 7-45 V operating supply range, 1.5 Arms continuous.
12	OUTB1	power_out	Full-bridge B power output, side B1; motor coil B terminal; 7-45 V operating supply range, 1.5 Arms continuous.
13	SENSEB2	power_out	Bridge B power-stage sense output (B2 side); connects to external shunt resistor for phase-current sensing; rated 1.5 Arms continuous.
14	SENSEB1	power_out	Bridge B power-stage sense output (B1 side); connects to external shunt resistor for phase-current sensing; rated 1.5 Arms continuous.
15	SNSB	input	Full-bridge B current-regulator sense input; voltage here is compared to the internal PWM reference; operating range −1 to +1 V, absolute maximum ±2 V.
16	~~{STBY}/~~{RESET}	input	Standby/reset input; forcing below VSTBYL (0.8 V max) disables the power stage, resets all control logic to power-up state, and reduces supply current to 45 µA max; normal operation requires >2 V; 60 kΩ internal pull-down.
17	~~{EN}/~~{FAULT}	bidirectional	Active-low power stage enable (logic input, 5 V compliant, 5 µA pull-down) with open-drain fault output; internal MOSFET pulls pin low on overcurrent, short-circuit, or thermal shutdown; VRELEASE = 0.6 V max, VOL = 0.3 V max at 4 mA; external REN/CEN programs re-enable delay.
18	DECAY	input	Decay mode selection; high (>2 V) selects slow-decay only (tOFF,SLOW = tOFF); low (<0.8 V) selects mixed decay (tOFF,SLOW = 5/8 × tOFF, tOFF,FAST = 3/8 × tOFF).
19	STCK	input	Step clock input; each rising edge advances or retards the microstepping sequencer by one step; maximum frequency 4 MHz, minimum high or low pulse width 20 ns.
20	DIR	input	Direction input; high increments the sequencer (forward), low decrements it (reverse); 20 ns setup time and 20 ns hold time required relative to STCK rising edge.
21	MODE1	input	Step-mode selection bit 1; combined with MODE2 and MODE3 selects full-step through 1/256-step resolution per Table 7; 20 ns setup/hold time required before STCK rising edge.
22	MODE2	input	Step-mode selection bit 2; combined with MODE1 and MODE3 selects full-step through 1/256-step resolution per Table 7; 20 ns setup/hold time required before STCK rising edge.
23	MODE3	input	Step-mode selection bit 3; combined with MODE1 and MODE2 selects full-step through 1/256-step resolution per Table 7; 20 ns setup/hold time required before STCK rising edge.
24	TOFF	input	PWM OFF-time adjustment pin; external resistor ROFF from this pin to GND sets total tOFF; recommended range 5 kΩ to 180 kΩ yielding approximately 10 µs to 150 µs; ROFF = 10 kΩ gives tOFF = 13 µs typical.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	QFN-24-EP(4x4)
Category	Motor Driver ICs
Pins	25

CAD (KiCad official)

Symbol: STSPIN820
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: stspin820-etched.step / stspin820-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stspin820.step / stspin820.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (29 pp, sha256 b1fd1d7e1b993fc0, retrieved 2026-09-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF