component
STS5P3LLH6
Public Made by Adomby adom
STMicroelectronics MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
| sts5p3llh6-etched.glb | 7d ago |
| sts5p3llh6-etched.step | 7d ago |
| sts5p3llh6-hero.glb | 7d ago |
| sts5p3llh6-hero.overlay.json | 7d ago |
| sts5p3llh6.glb | 7d ago |
| sts5p3llh6.kicad_mod | 7d ago |
| sts5p3llh6.kicad_sym | 7d ago |
| sts5p3llh6.lbr | 7d ago |
| sts5p3llh6.step | 7d ago |
| verification.json | 7d ago |
STS5P3LLH6
STMicroelectronics · MOSFETs · SO-8
STS5P3LLH6 from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with pins 2 and 3; VDS rating is 30 V. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 3; VDS rating is 30 V. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 2; VDS rating is 30 V. |
| 4 | G | input | Gate of the P-channel MOSFET with a maximum VGS of ±20 V and a threshold of 1.0 to 2.5 V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 6, 7 and 8; continuous ID of 5 A at 25 °C. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 7 and 8; continuous ID of 5 A at 25 °C. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 8; continuous ID of 5 A at 25 °C. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 7; continuous ID of 5 A at 25 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 30 | V | 2 | |||
| Gate-source voltage | VGS | -20 | 20 | V | 2 | ||
| Drain current (continuous) at Tamb = 25 °C | ID | 5 | A | Tamb = 25 °C | 2 | ||
| Drain current (continuous) at Tamb = 100 °C | ID | 3.2 | A | Tamb = 100 °C | 2 | ||
| Drain current (pulsed) | IDM | 20 | A | Pulse width limited by safe operating area | 2 | ||
| Total power dissipation | PTOT | 2.7 | W | Tamb = 25 °C | 2 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 2 | ||
| Operating junction temperature | TJ | 150 | °C | 2 | |||
| Thermal resistance, junction-to-ambient | RthJA | 47 | °C/W | Mounted on 1 inch² FR-4 board, 2 oz. Cu., t ≤ 10 s | 2 | ||
| Drain-source breakdown voltage | V(BR)DSS | 30 | V | VGS = 0 V, ID = 250 µA | 3 | ||
| Zero gate voltage drain current | IDSS | 1 | µA | VGS = 0 V, VDS = 30 V | 3 | ||
| Zero gate voltage drain current (125 °C) | IDSS | 10 | µA | VGS = 0 V, VDS = 30 V, TC = 125 °C | 3 | ||
| Gate-body leakage current | IGSS | 100 | nA | VDS = 0 V, VGS = ±20 V | 3 | ||
| Gate threshold voltage | VGS(th) | 1 | 2.5 | V | VDS = VGS, ID = 250 µA | 3 | |
| Static drain-source on-resistance | RDS(on) | 48 | 56 | mΩ | VGS = 10 V, ID = 2.5 A | 3 | |
| Static drain-source on-resistance | RDS(on) | 75 | 90 | mΩ | VGS = 4.5 V, ID = 2.5 A | 3 | |
| Forward on voltage | VSD | 1.1 | V | ISD = 5 A, VGS = 0 V | 3 | ||
| Input capacitance | Ciss | 639 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Output capacitance | Coss | 79 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Reverse transfer capacitance | Crss | 52 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Total gate charge | Qg | 6 | nC | VDD = 15 V, ID = 5 A, VGS = 4.5 V | 3 | ||
| Gate-source charge | Qgs | 1.9 | nC | VDD = 15 V, ID = 5 A, VGS = 4.5 V | 3 | ||
| Gate-drain charge | Qgd | 2.1 | nC | VDD = 15 V, ID = 5 A, VGS = 4.5 V | 3 | ||
| Turn-on delay time | td(on) | 5.4 | ns | VDD = 15 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Rise time | tr | 5 | ns | VDD = 15 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Turn-off delay time | td(off) | 19.2 | ns | VDD = 15 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Fall time | tf | 3.4 | ns | VDD = 15 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Reverse recovery time | trr | 11.2 | ns | ISD = 5 A, di/dt = 100 A/µs, VDD = 16 V, TJ = 150 °C | 3 | ||
| Reverse recovery charge | Qrr | 3.5 | nC | ISD = 5 A, di/dt = 100 A/µs, VDD = 16 V, TJ = 150 °C | 3 | ||
| Reverse recovery current | IRRM | 0.6 | A | ISD = 5 A, di/dt = 100 A/µs, VDD = 16 V, TJ = 150 °C | 3 |
CAD (KiCad official)
- Symbol:
STS5P3LLH6 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
sts5p3llh6-etched.step/sts5p3llh6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sts5p3llh6.step/sts5p3llh6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (13 pp, sha256
70d7d1add2c78f39, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).