main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers sts5n15f4: viewers · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/sts5n15f4 · Ray 2d ago
sts5n15f4-etched.glb sts5n15f4: factory component page (tier=mfr) · Ray 2d ago
sts5n15f4-etched.step sts5n15f4: factory component page (tier=mfr) · Ray 2d ago
sts5n15f4-hero.glb sts5n15f4: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
sts5n15f4-hero.overlay.json Publish 0.1.0 · Ray 2d ago
sts5n15f4.glb Publish 0.1.0 · Ray 2d ago
sts5n15f4.kicad_mod Publish 0.1.0 · Ray 2d ago
sts5n15f4.kicad_sym Publish 0.1.0 · Ray 2d ago
sts5n15f4.lbr Publish 0.1.0 · Ray 2d ago
sts5n15f4.step Publish 0.1.0 · Ray 2d ago

STS5N15F4

STMicroelectronics · MOSFETs · SO-8

STS5N15F4 from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET, one of three source pins (1-3) tied together internally.
2 S passive Source terminal of the N-channel MOSFET, one of three source pins (1-3) tied together internally.
3 S passive Source terminal of the N-channel MOSFET, one of three source pins (1-3) tied together internally.
4 G input Gate terminal; absolute maximum VGS is ±20 V and threshold VGS(th) is 2 V min to 4 V max at ID = 250 µA.
5 D passive Drain terminal, one of four drain pins (5-8) tied together; VDSS is 150 V and continuous ID is 5 A at TC = 25 °C.
6 D passive Drain terminal, one of four drain pins (5-8) tied together; VDSS is 150 V and continuous ID is 5 A at TC = 25 °C.
7 D passive Drain terminal, one of four drain pins (5-8) tied together; VDSS is 150 V and continuous ID is 5 A at TC = 25 °C.
8 D passive Drain terminal, one of four drain pins (5-8) tied together; VDSS is 150 V and continuous ID is 5 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: STS5N15F4
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: sts5n15f4-etched.step / sts5n15f4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sts5n15f4.step / sts5n15f4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (11 pp, sha256 0a1fe87c960c3935, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF