component
STPIC6D595MTR
Public Made by Adomby adom
STMicroelectronics Shift Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+52@@ -0,0 +1,52 @@+# STPIC6D595MTR++**STMicroelectronics** · Shift Registers · SO-16++STPIC6D595MTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC | power_in | Logic supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum). |+| 2 | SER IN | input | Serial data input to the 8-bit shift register, with setup and hold times of 10 ns min relative to the SRCK rising edge. |+| 3 | DRAIN0 | passive | Open-drain DMOS output 0, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 4 | DRAIN1 | passive | Open-drain DMOS output 1, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 5 | DRAIN2 | passive | Open-drain DMOS output 2, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 6 | DRAIN3 | passive | Open-drain DMOS output 3, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 7 | CLR | input | Active-low shift register clear: the input shift register is cleared when low, and data transfers to the storage register when high. |+| 8 | G | input | Active-low output enable: when high all output buffer data is held low and the drains are off, and when low the storage register data is transparent to the output buffer. |+| 9 | SER OUT | output | Serial output of the shift register that changes on the rising edge of SRCK, used for cascading to additional devices. |+| 10 | RCK | input | Register clock that transfers data from the shift register to the storage register. |+| 11 | DRAIN4 | passive | Open-drain DMOS output 4, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 12 | DRAIN5 | passive | Open-drain DMOS output 5, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 13 | DRAIN6 | passive | Open-drain DMOS output 6, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 14 | DRAIN7 | passive | Open-drain DMOS output 7, rated 20 V with 100 mA continuous sink current and 250 mA current limit. |+| 15 | SRCK | input | Shift register clock that shifts data in on the rising edge, with a minimum pulse duration of 40 ns. |+| 16 | GND | power_in | Ground reference; each power DMOS source is internally connected to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `STPIC6D595MTR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SO-16 (KiCad packages3D, STEP)+- 3D model files: `stpic6d595mtr-etched.step` / `stpic6d595mtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stpic6d595mtr.step` / `stpic6d595mtr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885432910155776) (21 pp, sha256 `188a3dfa7eff0232`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stpic6d595mtr-datasheet.pdf)
page.jsonadded+209@@ -0,0 +1,209 @@+{+ "slug": "stpic6d595mtr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Shift Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "stpic6d595mtr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stpic6d595mtr.kicad_sym",+ "stpic6d595mtr.kicad_mod",+ "stpic6d595mtr.glb",+ "stpic6d595mtr.step",+ "stpic6d595mtr.lbr",+ "docs/hero.png",+ "docs/stpic6d595mtr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "stpic6d595mtr-hero.glb",+ "stpic6d595mtr-hero.overlay.json"+ ],+ "component": {+ "mpn": "STPIC6D595MTR",+ "manufacturer": "STMicroelectronics",+ "package": "SO-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885432910155776",+ "parts": {+ "symbol": "stpic6d595mtr.kicad_sym",+ "footprint": "stpic6d595mtr.kicad_mod",+ "model_3d": "stpic6d595mtr-hero.glb",+ "model_3d_plain": "stpic6d595mtr.glb",+ "model_3d_step": "stpic6d595mtr-etched.step",+ "model_3d_step_plain": "stpic6d595mtr.step",+ "lbr": "stpic6d595mtr.lbr"+ },+ "distributor_links": {+ "lcsc": 495247,+ "digikey": "497-6329-2-ND",+ "mouser": "511-STPIC6D595MTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T00:48:57Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-6329-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-STPIC6D595MTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VCC",+ "type": "power_in",+ "description": "Logic supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum)."+ },+ {+ "number": "2",+ "name": "SER IN",+ "type": "input",+ "description": "Serial data input to the 8-bit shift register, with setup and hold times of 10 ns min relative to the SRCK rising edge."+ },+ {+ "number": "3",+ "name": "DRAIN0",+ "type": "passive",+ "description": "Open-drain DMOS output 0, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "4",+ "name": "DRAIN1",+ "type": "passive",+ "description": "Open-drain DMOS output 1, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "5",+ "name": "DRAIN2",+ "type": "passive",+ "description": "Open-drain DMOS output 2, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "6",+ "name": "DRAIN3",+ "type": "passive",+ "description": "Open-drain DMOS output 3, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "7",+ "name": "CLR",+ "type": "input",+ "description": "Active-low shift register clear: the input shift register is cleared when low, and data transfers to the storage register when high."+ },+ {+ "number": "8",+ "name": "G",+ "type": "input",+ "description": "Active-low output enable: when high all output buffer data is held low and the drains are off, and when low the storage register data is transparent to the output buffer."+ },+ {+ "number": "9",+ "name": "SER OUT",+ "type": "output",+ "description": "Serial output of the shift register that changes on the rising edge of SRCK, used for cascading to additional devices."+ },+ {+ "number": "10",+ "name": "RCK",+ "type": "input",+ "description": "Register clock that transfers data from the shift register to the storage register."+ },+ {+ "number": "11",+ "name": "DRAIN4",+ "type": "passive",+ "description": "Open-drain DMOS output 4, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "12",+ "name": "DRAIN5",+ "type": "passive",+ "description": "Open-drain DMOS output 5, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "13",+ "name": "DRAIN6",+ "type": "passive",+ "description": "Open-drain DMOS output 6, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "14",+ "name": "DRAIN7",+ "type": "passive",+ "description": "Open-drain DMOS output 7, rated 20 V with 100 mA continuous sink current and 250 mA current limit."+ },+ {+ "number": "15",+ "name": "SRCK",+ "type": "input",+ "description": "Shift register clock that shifts data in on the rising edge, with a minimum pulse duration of 40 ns."+ },+ {+ "number": "16",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; each power DMOS source is internally connected to GND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Datasheet shows one pin configuration figure (Figure 1) without a package label. I assumed it applie; Drain pins are typed passive because open-drain outputs have no exact KiCad class in the schema. Cha",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 21,+ "cost_usd": 0.3088,+ "at": "2026-10-03T00:48:39"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885432910155776",+ "pages": 21,+ "sha256": "188a3dfa7eff0232",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}