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STP65N150M9

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by adom

STMicroelectronics MOSFETs, TO-220. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Ray stp65n150m9: specified limits as data (metadata.characteristics, 22 rows from the datasheet) 5c0be48 16d ago

STP65N150M9

STMicroelectronics · MOSFETs · TO-220

STP65N150M9 from STMicroelectronics, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate terminal of the MOSFET; the gate-source voltage is rated ±30 V (absolute maximum, Table 1).
2 D passive Drain terminal, electrically connected to the metal tab (TAB); drain-source breakdown voltage is 650 V minimum (V(BR)DSS, Table 4).
3 S passive Source terminal of the MOSFET; continuous drain current is rated 20 A at TC = 25 °C (Table 1).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-220
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-source voltage VGS -30 30 V 2
Drain current (continuous) at TC = 25 °C ID 20 A TC = 25 °C 2
Drain current (continuous) at TC = 100 °C ID 12.5 A TC = 100 °C 2
Drain current (pulsed) IDM 60 A Pulse width limited by safe operating area 2
Total power dissipation at TC = 25 °C PTOT 140 W TC = 25 °C 2
Peak diode recovery voltage slope dv/dt(2) 50 V/ns ISD ≤ 10 A, VDS (peak) < V(BR)DSS, VDD = 400 V 2
Peak diode recovery current slope di/dt(2) 900 A/μs ISD ≤ 10 A, VDS (peak) < V(BR)DSS, VDD = 400 V 2
MOSFET dv/dt ruggedness dv/dt(3) 120 V/ns VDS (peak) < V(BR)DSS, VDD ≤ 400 V 2
Storage temperature range Tstg -55 150 °C 2
Thermal resistance, junction-to-case RthJC 0.89 °C/W 2
Thermal resistance, junction-to-ambient RthJA 62.5 °C/W 2
Avalanche current, repetitive or non-repetitive IAR 4 A Pulse width limited by TJ max. 2
Single pulse avalanche energy EAS 200 mJ Starting TJ = 25 °C, ID = IAR, VDD = 50 V 2
Drain-source breakdown voltage V(BR)DSS 650 V VGS = 0 V, ID = 1 mA 3
Zero gate voltage drain current IDSS 1 µA VGS = 0 V, VDS = 650 V 3
Zero gate voltage drain current at TC = 125 °C IDSS 200 µA VGS = 0 V, VDS = 650 V, TC = 125 °C (specified by design, not tested in production) 3
Gate-body leakage current IGSS -5 5 µA VDS = 0 V, VGS = ±25 V 3
Gate threshold voltage VGS(th) 3.2 3.7 4.2 V VDS = VGS, ID = 250 µA 3
Static drain-source on-resistance RDS(on) 128 150 mΩ VGS = 10 V, ID = 10 A 3
Source-drain current ISD 20 A 4
Source-drain current (pulsed) ISDM 60 A Pulse width limited by safe operating area 4
Forward on voltage VSD 1.6 V ISD = 20 A, VGS = 0 V (pulsed: pulse duration = 300 µs, duty cycle 1.5%) 4

CAD (KiCad official)

  • Symbol: STP65N150M9
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220 (KiCad packages3D, STEP)
  • 3D model files: stp65n150m9-etched.step / stp65n150m9-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stp65n150m9.step / stp65n150m9.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (14 pp, sha256 97ba024a7259b57a, retrieved 2026-10-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF