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STP45N40DM2AG

STMicroelectronics · MOSFETs · TO-220

STP45N40DM2AG from STMicroelectronics, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; Zener-protected with V(BR)GSO of ±30 V min and an absolute maximum VGS of ±25 V, with a gate threshold of 3 V min, 4 V typ and 5 V max at ID = 250 µA.
2 D passive Drain, connected internally to the TAB; V(BR)DSS is 400 V min, continuous ID is 38 A at Tcase = 25 °C, and pulsed IDM is 152 A.
3 S passive Source; continuous body-diode current ISD is 38 A and pulsed ISDM is 152 A.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-220
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: STP45N40DM2AG
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220 (KiCad packages3D, STEP)
  • 3D model files: stp45n40dm2ag-etched.step / stp45n40dm2ag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stp45n40dm2ag.step / stp45n40dm2ag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (13 pp, sha256 54ac511e69fb67c3, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF