# STP4435

**STANSON Tech** · MOSFETs · SOP-8

STP4435 from STANSON Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET; internally tied to pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET; internally tied to pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET; internally tied to pins 1 and 2. |
| 4 | G | input | Gate; threshold VGS(th) -1.0 V min to -3.0 V max, absolute maximum VGSS ±20 V. |
| 5 | D | passive | Drain; VDSS -30 V, continuous ID -10.0 A at TA=25℃, shorted to pins 6, 7 and 8. |
| 6 | D | passive | Drain; VDSS -30 V, continuous ID -10.0 A at TA=25℃, shorted to pins 5, 7 and 8. |
| 7 | D | passive | Drain; VDSS -30 V, continuous ID -10.0 A at TA=25℃, shorted to pins 5, 6 and 8. |
| 8 | D | passive | Drain; VDSS -30 V, continuous ID -10.0 A at TA=25℃, shorted to pins 5, 6 and 7. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STANSON Tech |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | -30 |  |  | V | VGS=0V, ID=-250uA | 3 |
| Gate Threshold Voltage | VGS(th) | -1 |  | -3 | V | VDS=VGS, ID=-250 uA | 3 |
| Gate Leakage Current | IGSS | -100 |  | 100 | nA | VDS=0V, VGS=±20V | 3 |
| Zero Gate Voltage Drain Current (TJ=55℃) | IDSS |  |  | -1 | uA | TJ=55℃, VDS=-30V, VGS=0V | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -5 | uA | VDS=-30V, VGS=0V | 3 |
| Drain-source On-Resistance | RDS(on) |  | 0.022 | 0.03 | Ω | VGS=-10V, ID=-9.2A | 3 |
| Drain-source On-Resistance | RDS(on) |  | 0.028 | 0.035 | Ω | VGS=-4.5V, ID=-7.0 | 3 |
| Forward Transconductance | gfs |  | 24 |  | S | VDS=-10V, ID=-9.0A | 3 |
| Diode Forward Voltage | VSD |  | -0.8 | -1 | V | IS=-2.0A, VGS=0V | 3 |
| Total Gate Charge | Qg |  | 16 | 24 | nC | VDS=-15V, VGS=-10V, ID≡-9.A | 3 |
| Gate-Source Charge | Qgs |  | 2.3 |  | nC | VDS=-15V, VGS=-10V, ID≡-9.A | 3 |
| Gate-Drain Charge | Qgd |  | 4.5 |  | nC | VDS=-15V, VGS=-10V, ID≡-9.A | 3 |
| Input Capacitance | Ciss |  | 1650 |  | pF | VDS=-15V, VGS=0V, f=1MHz | 3 |
| Output Capacitance | Coss |  | 350 |  | pF | VDS=-15V, VGS=0V, f=1MHz | 3 |
| Reverse Transfer Capacitance | Crss |  | 235 |  | pF | VDS=-15V, VGS=0V, f=1MHz | 3 |
| Turn-On Delay Time | td(on) |  | 16 | 30 | nS | VDD=15V, RL=15Ω, ID=-1.0A, VGEN=-10V, RG=6Ω | 3 |
| Turn-On Rise Time | tr |  | 17 | 30 | nS | VDD=15V, RL=15Ω, ID=-1.0A, VGEN=-10V, RG=6Ω | 3 |
| Turn-Off Delay Time | td(off) |  | 65 | 110 | nS | VDD=15V, RL=15Ω, ID=-1.0A, VGEN=-10V, RG=6Ω | 3 |
| Turn-Off Fall Time | tf |  | 35 | 80 | nS | VDD=15V, RL=15Ω, ID=-1.0A, VGEN=-10V, RG=6Ω | 3 |
| Drain-Source Voltage | VDSS |  | -30 |  | V | Ta = 25℃ unless otherwise noted | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V | Ta = 25℃ unless otherwise noted | 2 |
| Continuous Drain Current (TJ=150℃, TA=25℃) | ID |  | -10 |  | A | TJ=150℃, TA=25℃ | 2 |
| Continuous Drain Current (TA=70℃) | ID |  | -7 |  | A | TA=70℃ | 2 |
| Pulsed Drain Current | IDM |  | -50 |  | A |  | 2 |
| Continuous Source Current (Diode Conduction) | IS |  | -2.3 |  | A |  | 2 |
| Power Dissipation (TA=25℃) | PD |  | 2.8 |  | W | TA=25℃ | 2 |
| Power Dissipation (TA=70℃) | PD |  | 1.8 |  | W | TA=70℃ | 2 |
| Operation Junction Temperature | TJ | -55 |  | 150 | ℃ |  | 2 |
| Storage Temperature Range | TSTG | -55 |  | 150 | ℃ |  | 2 |
| Thermal Resistance, Junction to Ambient | RθJA |  | 70 |  | ℃/W |  | 2 |

## CAD (KiCad official)

- Symbol: `STP4435`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `stp4435-etched.step` / `stp4435-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stp4435.step` / `stp4435.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STANSON Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907494076780544) (6 pp, sha256 `257ab5a7393dfea7`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stp4435-datasheet.pdf)