component
STP110N8F6
Public Made by Adomby adom
STMicroelectronics MOSFETs, TO-220. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+39@@ -0,0 +1,39 @@+# STP110N8F6++**STMicroelectronics** · MOSFETs · TO-220++STP110N8F6 from STMicroelectronics, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Gate | input | Gate control terminal rated for ±20 V gate-source voltage maximum. |+| 2 | Drain | passive | Drain terminal rated for 110 A continuous drain current at TC = 25 °C and maximum VDS of 80 V. |+| 3 | Source | passive | Source terminal with integrated body diode forward voltage of 1.2 V at ISD = 110 A. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | TO-220 |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `STP110N8F6`+- Footprint: `Package_TO_SOT_THT:TO-220-3_Vertical`+- 3D model: TO-220 (KiCad packages3D, STEP)+- 3D model files: `stp110n8f6-etched.step` / `stp110n8f6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stp110n8f6.step` / `stp110n8f6.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887270091075584) (13 pp, sha256 `d5bf490bf14053b4`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stp110n8f6-datasheet.pdf)
page.jsonadded+113@@ -0,0 +1,113 @@+{+ "slug": "stp110n8f6",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics MOSFETs, TO-220. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "transistors-thyristors",+ "stp110n8f6",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stp110n8f6.kicad_sym",+ "stp110n8f6.kicad_mod",+ "stp110n8f6.glb",+ "stp110n8f6.step",+ "stp110n8f6.lbr",+ "docs/hero.png",+ "docs/stp110n8f6-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "STP110N8F6",+ "manufacturer": "STMicroelectronics",+ "package": "TO-220",+ "pin_count": 3,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887270091075584",+ "parts": {+ "symbol": "stp110n8f6.kicad_sym",+ "footprint": "stp110n8f6.kicad_mod",+ "model_3d": "stp110n8f6-etched.glb",+ "model_3d_plain": "stp110n8f6.glb",+ "model_3d_step": "stp110n8f6-etched.step",+ "model_3d_step_plain": "stp110n8f6.step",+ "lbr": "stp110n8f6.lbr"+ },+ "distributor_links": {+ "lcsc": "C81146"+ },+ "pins": [+ {+ "number": "1",+ "name": "Gate",+ "type": "input",+ "description": "Gate control terminal rated for ±20 V gate-source voltage maximum."+ },+ {+ "number": "2",+ "name": "Drain",+ "type": "passive",+ "description": "Drain terminal rated for 110 A continuous drain current at TC = 25 °C and maximum VDS of 80 V."+ },+ {+ "number": "3",+ "name": "Source",+ "type": "passive",+ "description": "Source terminal with integrated body diode forward voltage of 1.2 V at ISD = 110 A."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-to-terminal assignment inferred from internal schematic diagram (page 1) which labels G, D, S te"+ ],+ "pages_sent": 13,+ "cost_usd": 0.066,+ "at": "2026-09-22T17:32:16"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887270091075584",+ "pages": 13,+ "sha256": "d5bf490bf14053b4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 3,+ "described": 3,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}