STN4828-HXY

{
  "slug": "stn4828-hxy",
  "version": "0.1.0",
  "type": "component",
  "description": "HXY MOSFET MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "transistors-thyristors",
    "stn4828-hxy",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "stn4828-hxy.kicad_sym",
    "stn4828-hxy.kicad_mod",
    "stn4828-hxy.glb",
    "stn4828-hxy.step",
    "stn4828-hxy.lbr",
    "docs/hero.png",
    "docs/stn4828-hxy-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "stn4828-hxy-hero.glb",
    "stn4828-hxy-hero.overlay.json",
    "stn4828-hxy-etched.glb"
  ],
  "component": {
    "mpn": "STN4828-HXY",
    "manufacturer": "HXY MOSFET",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590909211817955328",
    "parts": {
      "symbol": "stn4828-hxy.kicad_sym",
      "footprint": "stn4828-hxy.kicad_mod",
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      "model_3d_plain": "stn4828-hxy-etched.glb",
      "model_3d_step": "stn4828-hxy-etched.step",
      "model_3d_step_plain": "stn4828-hxy.step",
      "lbr": "stn4828-hxy.lbr"
    },
    "distributor_links": {
      "lcsc": "C22366494"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T14:35:36Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "S1",
        "type": "passive",
        "description": "Source terminal of N-channel MOSFET 1; the datasheet gives no pin-specific limit, so the device ratings apply (VDS 60 V, VGS ±20 V)."
      },
      {
        "number": "2",
        "name": "G1",
        "type": "input",
        "description": "Gate terminal of N-channel MOSFET 1; gate-source voltage is rated ±20 V and the threshold VGS(th) is 1.0 to 2.0 V."
      },
      {
        "number": "3",
        "name": "S2",
        "type": "passive",
        "description": "Source terminal of N-channel MOSFET 2; the datasheet gives no pin-specific limit, so the device ratings apply (VDS 60 V, VGS ±20 V)."
      },
      {
        "number": "4",
        "name": "G2",
        "type": "input",
        "description": "Gate terminal of N-channel MOSFET 2; gate-source voltage is rated ±20 V and the threshold VGS(th) is 1.0 to 2.0 V."
      },
      {
        "number": "5",
        "name": "D2",
        "type": "passive",
        "description": "Drain terminal of N-channel MOSFET 2; drain-source voltage is rated 60 V and drain current 6.5 A at TA=25°C."
      },
      {
        "number": "6",
        "name": "D2",
        "type": "passive",
        "description": "Drain terminal of N-channel MOSFET 2 (internally common with pin 5); drain-source voltage is rated 60 V and drain current 6.5 A at TA=25°C."
      },
      {
        "number": "7",
        "name": "D1",
        "type": "passive",
        "description": "Drain terminal of N-channel MOSFET 1 (internally common with pin 8); drain-source voltage is rated 60 V and drain current 6.5 A at TA=25°C."
      },
      {
        "number": "8",
        "name": "D1",
        "type": "passive",
        "description": "Drain terminal of N-channel MOSFET 1; drain-source voltage is rated 60 V and drain current 6.5 A at TA=25°C."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pinout comes from the pin-label diagram on page 1 (top row 1-4 = S1 G1 S2 G2, bottom row 8-5 = D; The datasheet gives no per-pin electrical limits. The pin descriptions use device-level ratings from; Pin types are inferred from the MOSFET function (gate = input, drain/source = passive) and are not s"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0396,
        "at": "2026-10-17T14:33:21"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590909211817955328",
        "pages": 7,
        "sha256": "fd02a1e5df7a5c25",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "stn4828-hxy-etched.step",
        "role": "eda",
        "up": "Z",
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        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "116a5718e08edb3d3397a12024e4a5ae9492324f4847c88cc3dae95fb4007212",
        "checked": "2026-10-17",
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}