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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM8S903K3T6C

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8S903K3T6C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	input	Reset input with internal 30-80kΩ weak pull-up resistor (55kΩ typical), 75ns schmitt trigger filter, and open-drain output capability to drive output low at 0.5V (3mA max).
2	PA1/OSCIN	bidirectional	Port A1 GPIO or 1-16MHz HSE oscillator/external clock input with ±1µA leakage current; automatically configured as input weak pull-up during reset and halt modes.
3	PA2/OSCOUT	bidirectional	Port A2 GPIO or HSE oscillator output for 16MHz crystal resonator feedback (1.2-6mA current dependent on load capacitance, startup time <1ms).
4	VSS	power_in	Digital ground reference for core, I/O, and analog circuits; all VSS pins must be connected to external power supply ground.
5	VCAP	passive	External capacitor connection point for 1.8V on-chip voltage regulator requiring 470-3300nF with ESR <0.3Ω and ESL <15nH.
6	VDD	power_in	Digital power supply for microcontroller core, peripherals, and I/O circuits with 2.95-5.5V operating voltage range; all VDD pins must be connected.
7	PA3/TIM5_CH3[SPI_NSS][UART1_TX]	bidirectional	Port A3 high-sink GPIO output (10mA @ 2.0V, 20mA @ 1.5V source; 10mA @ 0.8V, 20mA @ 1.5V sink) with programmable fast/slow speed; Timer5_CH3, SPI slave select, or UART1_TX via remapping.
8	PF4[UART1_RX]	bidirectional	Port F4 GPIO with standard push-pull output (10mA @ 2.1V source at 3.3V VDD); UART1 receive data input when AFR1:0 alternate function remapping enabled.
9	PB7	bidirectional	Port B7 GPIO with standard push-pull output and floating input configuration; supports Port B external interrupt detection.
10	PB6	bidirectional	Port B6 GPIO with standard push-pull output and floating input configuration; supports Port B external interrupt detection.
11	PB5/I2C_SDA[TIM1_BKIN]	bidirectional	Port B5 GPIO or I2C serial data line with true open-drain output (no internal pull-up or protection diode) and 300ns internal SDA hold time; Timer1 break input via AFR4 remapping.
12	PB4/I2C_SCL[ADC_ETR]	bidirectional	Port B4 GPIO or I2C serial clock line with true open-drain output (no internal pull-up or protection diode) and 300ns SDA setup/hold timing; ADC external trigger input via AFR4 remapping.
13	PB3/AIN3/TIM1_ETR	bidirectional	Port B3 high-sink GPIO; analog input channel AIN3 (0-VDD range) with programmable upper/lower thresholds for analog watchdog; Timer1 external trigger input.
14	PB2/AIN2/TIM1_CH3N	bidirectional	Port B2 high-sink GPIO; analog input channel AIN2 (0-VDD range) with ±2LSB typical accuracy at fADC=4MHz; Timer1 inverted channel 3 complementary output.
15	PB1/AIN1/TIM1_CH2N	bidirectional	Port B1 high-sink GPIO; analog input channel AIN1 (0-VDD range) with ±2LSB typical accuracy at fADC=4MHz; Timer1 inverted channel 2 complementary output.
16	PB0/AIN0/TIM1_CH1N	bidirectional	Port B0 high-sink GPIO; analog input channel AIN0 (0-VDD range) with ±2LSB typical accuracy at fADC=4MHz; Timer1 inverted channel 1 complementary output.
17	PE5/SPI_NSS[TIM1_CH1N]	bidirectional	Port E5 high-sink GPIO with programmable fast/slow output; SPI master/slave select input/output (0-8Mbps); Timer1 inverted channel 1 via AFR1:0 remapping.
18	PC1/TIM1_CH1/UART1_CK[TIM1_CH2N]	bidirectional	Port C1 high-sink GPIO; Timer1 channel 1 output compare/PWM (edge and center-aligned modes); UART1 clock output; Timer1 inverted CH2 via AFR1:0 remapping.
19	PC2/TIM1_CH2[TIM1_CH3N]	bidirectional	Port C2 high-sink GPIO with programmable fast/slow output; Timer1 channel 2 output compare/PWM; Timer1 inverted channel 3 via AFR1:0 remapping.
20	PC3/TIM1_CH3/TLI/[TIM1_CH1N]	bidirectional	Port C3 high-sink GPIO; Timer1 channel 3 output compare/PWM; top-level interrupt input with dedicated priority; Timer1 inverted CH1 via AFR7 remapping.
21	PC4/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]	bidirectional	Port C4 high-sink GPIO (10mA @ 2.1V, 20mA @ 3.3V source); Timer1 channel 4 output; configurable clock output (HSI/HSE/fMASTER÷2); analog input AIN2; Timer1 inverted CH2 via AFR7.
22	PC5/SPI_SCK[TIM5_CH1]	bidirectional	Port C5 high-sink GPIO; SPI serial clock (0-8Mbps master mode, 0-7Mbps slave mode) with configurable CPOL/CPHA; Timer5 channel 1 via AFR0 remapping.
23	PC6/SPI_MOSI[TIM1_CH1]	bidirectional	Port C6 high-sink GPIO; SPI master-out/slave-in data line (0-8Mbps) with 5ns minimum setup time; Timer1 channel 1 output via AFR0 remapping.
24	PC7/SPI_MISO[TIM1_CH2]	bidirectional	Port C7 high-sink GPIO; SPI master-in/slave-out data line (0-8Mbps) with 3×tMASTER max access time from SCK rising edge; Timer1 channel 2 via AFR0 remapping.
25	PD0/TIM1_BKIN[CLK_CCO]	bidirectional	Port D0 high-sink GPIO with programmable fast/slow output; Timer1 break input to force PWM outputs to inactive state; configurable clock output via AFR5 remapping.
26	PD1/SWIM	bidirectional	Port D1 high-sink GPIO with programmable fast/slow output or SWIM single-wire interface module for debug/in-circuit programming; input weak pull-up during reset and after reset release.
27	PD2/AIN3/[TIM5_CH3]	bidirectional	Port D2 high-sink GPIO; analog input channel AIN3 (0-VDD range) with ±2LSB typical accuracy at fADC=4MHz; Timer5 channel 3 via AFR2 or AFR1 remapping.
28	PD3/AIN4/TIM5_CH2/ADC_ETR	bidirectional	Port D3 high-sink GPIO; analog input channel AIN4 (0-VDD range) with ±2LSB typical accuracy; Timer5 channel 2 output; ADC external trigger input.
29	PD4/TIM5_CH1/BEEP[UART1_CK]	bidirectional	Port D4 high-sink GPIO with programmable fast/slow output; Timer5 channel 1 output; beeper output (1/2/4kHz selectable) via AFR7 remapping; UART1 clock via AFR2.
30	PD5/AIN5/UART1_TX	bidirectional	Port D5 high-sink GPIO; analog input channel AIN5 (0-VDD range) with ±2LSB typical accuracy; UART1 transmit data output (NRZ format, 1Mbps max).
31	PD6/AIN6/UART1_RX	bidirectional	Port D6 high-sink GPIO; analog input channel AIN6 (0-VDD range) with ±2LSB typical accuracy; UART1 receive data input (NRZ format, 1Mbps max).
32	PD7/TLI[TIM1_CH4]	bidirectional	Port D7 high-sink GPIO with programmable fast/slow output; top-level interrupt input (dedicated priority level); Timer1 channel 4 output compare/PWM via AFR6 remapping.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-32(7x7)
Category	Embedded Processors & Controllers
Pins	32

CAD (KiCad official)

Symbol: STM8S903K3T6C
Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
3D model files: stm8s903k3t6c-etched.step / stm8s903k3t6c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s903k3t6c.step / stm8s903k3t6c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (121 pp, sha256 ec1018977a2287d4, retrieved 2026-09-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF