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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM8S208RBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM8S208RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	bidirectional	Reset pin listed as I/O with the Reset function in the pin table; its electrical characteristics are given in Table 41 (section 10.3.7).
2	PA1/OSCIN	bidirectional	Port A1 I/O that doubles as the resonator/crystal input OSCIN, with speed O1 (slow, up to 2 MHz).
3	PA2/OSCOUT	bidirectional	Port A2 I/O that doubles as the resonator/crystal output OSCOUT, with speed O1 (slow, up to 2 MHz).
4	VSSIO_1	power_in	I/O ground.
5	VSS	power_in	Digital ground.
6	VCAP	passive	1.8 V regulator capacitor pin, which requires the external VCAP capacitor specified in section 10.3.1.
7	VDD	power_in	Digital power supply, with an operating voltage of 2.95 to 5.5 V as stated in the features.
8	VDDIO_1	power_in	I/O power supply.
9	PA3/TIM2_CH3	bidirectional	Port A3 I/O with Timer 2 channel 3 as the default alternate function and TIM3_CH1 as the alternate function after AFR1 remapping.
10	PA4/UART1_RX	bidirectional	Port A4 I/O with UART1 receive as the default alternate function, high sink capable (HS), and pulled up by the ROM bootloader during activation before returning to floating.
11	PA5/UART1_TX	bidirectional	Port A5 I/O with UART1 transmit as the default alternate function, and high sink capable (HS).
12	PA6/UART1_CK	bidirectional	Port A6 I/O with UART1 synchronous clock as the default alternate function, and high sink capable (HS).
13	PF7/AIN15	bidirectional	Port F7 I/O with analog input 15, with speed O1 (slow, up to 2 MHz).
14	PF6/AIN14	bidirectional	Port F6 I/O with analog input 14, with speed O1 (slow, up to 2 MHz).
15	PF5/AIN13	bidirectional	Port F5 I/O with analog input 13, with speed O1 (slow, up to 2 MHz).
16	PF4/AIN12	bidirectional	Port F4 I/O with analog input 12, with speed O1 (slow, up to 2 MHz).
17	PF3/AIN11	bidirectional	Port F3 I/O with analog input 11, with speed O1 (slow, up to 2 MHz).
18	VREF+	power_in	ADC positive reference voltage.
19	VDDA	power_in	Analog power supply.
20	VSSA	power_in	Analog ground.
21	VREF-	power_in	ADC negative reference voltage.
22	PF0/AIN10	bidirectional	Port F0 I/O with analog input 10, with speed O1 (slow, up to 2 MHz).
23	PB7/AIN7	bidirectional	Port B7 I/O with analog input 7, with speed O1 (slow, up to 2 MHz).
24	PB6/AIN6	bidirectional	Port B6 I/O with analog input 6, with speed O1 (slow, up to 2 MHz).
25	PB5/AIN5	bidirectional	Port B5 I/O with analog input 5, and I2C_SDA available as the alternate function after AFR6 remapping.
26	PB4/AIN4	bidirectional	Port B4 I/O with analog input 4, and I2C_SCL available as the alternate function after AFR6 remapping.
27	PB3/AIN3	bidirectional	Port B3 I/O with analog input 3, and TIM1_ETR available as the alternate function after AFR5 remapping.
28	PB2/AIN2	bidirectional	Port B2 I/O with analog input 2, and TIM1_CH3N available as the alternate function after AFR5 remapping.
29	PB1/AIN1	bidirectional	Port B1 I/O with analog input 1, and TIM1_CH2N available as the alternate function after AFR5 remapping.
30	PB0/AIN0	bidirectional	Port B0 I/O with analog input 0, and TIM1_CH1N available as the alternate function after AFR5 remapping.
31	PE7/AIN8	bidirectional	Port E7 I/O with analog input 8, with speed O1 (slow, up to 2 MHz).
32	PE6/AIN9	bidirectional	Port E6 I/O with analog input 9, with speed O1 (slow, up to 2 MHz).
33	PE5/SPI_NSS	bidirectional	Port E5 I/O with the SPI master/slave select function, with speed O1 (slow, up to 2 MHz).
34	PC1/TIM1_CH1	bidirectional	Port C1 I/O, high sink capable (HS), with Timer 1 channel 1 as the alternate function.
35	PC2/TIM1_CH2	bidirectional	Port C2 I/O, high sink capable (HS), with Timer 1 channel 2 as the alternate function.
36	PC3/TIM1_CH3	bidirectional	Port C3 I/O, high sink capable (HS), with Timer 1 channel 3 as the alternate function.
37	PC4/TIM1_CH4	bidirectional	Port C4 I/O, high sink capable (HS), with Timer 1 channel 4 as the alternate function.
38	PC5/SPI_SCK	bidirectional	Port C5 I/O, high sink capable (HS), with the SPI clock as the alternate function.
39	VSSIO_2	power_in	I/O ground.
40	VDDIO_2	power_in	I/O power supply.
41	PC6/SPI_MOSI	bidirectional	Port C6 I/O, high sink capable (HS), with the SPI master out / slave in function as the alternate function.
42	PC7/SPI_MISO	bidirectional	Port C7 I/O, high sink capable (HS), with the SPI master in / slave out function as the alternate function.
43	PG0/CAN_TX	bidirectional	Port G0 I/O with beCAN transmit as the alternate function, which is available on STM8S208xx devices only.
44	PG1/CAN_RX	bidirectional	Port G1 I/O with beCAN receive as the alternate function, which is available on STM8S208xx devices only.
45	PG2	bidirectional	Port G2 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
46	PG3	bidirectional	Port G3 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
47	PG4	bidirectional	Port G4 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
48	PI0	bidirectional	Port I0 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
49	PG5	bidirectional	Port G5 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
50	PG6	bidirectional	Port G6 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
51	PG7	bidirectional	Port G7 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
52	PE4	bidirectional	Port E4 general-purpose I/O, with speed O1 (slow, up to 2 MHz).
53	PE3/TIM1_BKIN	bidirectional	Port E3 I/O with the Timer 1 break input as the alternate function, with speed O1 (slow, up to 2 MHz).
54	PE2/I2C_SDA	bidirectional	Port E2 true open-drain I/O (T, with no P-buffer and no protection diode to VDD) used as the I2C data line.
55	PE1/I2C_SCL	bidirectional	Port E1 true open-drain I/O (T, with no P-buffer and no protection diode to VDD) used as the I2C clock line.
56	PE0/CLK_CCO	bidirectional	Port E0 I/O, high sink capable (HS), with the configurable clock output (CLK_CCO) as the alternate function.
57	PD0/TIM3_CH2	bidirectional	Port D0 I/O, high sink capable (HS), with Timer 3 channel 2 as default; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are the alternates after remapping.
58	PD1/SWIM	bidirectional	Port D1 I/O, high sink capable (HS), serving as the SWIM data interface, and it is input pull-up during the reset phase and after internal reset release.
59	PD2/TIM3_CH1	bidirectional	Port D2 I/O, high sink capable (HS), with Timer 3 channel 1 as default and TIM2_CH3 (AFR1) as the alternate after remapping.
60	PD3/TIM2_CH2	bidirectional	Port D3 I/O, high sink capable (HS), with Timer 2 channel 2 as default and ADC_ETR (AFR0) as the alternate after remapping.
61	PD4/TIM2_CH1/BEEP	bidirectional	Port D4 I/O, high sink capable (HS), with Timer 2 channel 1 as default and the BEEP output (AFR7) as the alternate after remapping.
62	PD5/UART3_TX	bidirectional	Port D5 I/O with UART3 data transmit as the alternate function, with speed O1 (slow, up to 2 MHz).
63	PD6/UART3_RX	bidirectional	Port D6 I/O with UART3 data receive as the alternate function, whose default state is controlled by the ROM bootloader and returned to floating before a return from the bootloader.
64	PD7/TLI	bidirectional	Port D7 I/O with the top level interrupt (TLI) as the function; the TIM1_CH4 (AFR4) remap is reserved on this package and must be kept at 0.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: STM8S208RBT6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm8s208rbt6-etched.step / stm8s208rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s208rbt6.step / stm8s208rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (117 pp, sha256 7adeaa849cf9e22f, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF