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STM8S208C8T6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S208C8T6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM8S208C8T6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (marked I/O in Table 6) with reset state X after internal reset release. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O with slow output speed O1 (up to 2 MHz) that serves as the resonator/crystal oscillator input OSCIN. |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O with slow output speed O1 (up to 2 MHz) that serves as the resonator/crystal oscillator output OSCOUT. |
| 4 | VSSIO_1 | power_in | I/O ground supply for the first I/O group. |
| 5 | VSS | power_in | Digital ground. |
| 6 | VCAP | passive | Connection for the 1.8 V regulator capacitor. |
| 7 | VDD | power_in | Digital power supply. |
| 8 | VDDIO_1 | power_in | I/O power supply for the first I/O group. |
| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O whose default alternate function is Timer 2 channel 3 (TIM2_CH3); TIM3_CH1 is available as a remapped alternate function via option bit AFR1. |
| 10 | PA4/UART1_RX | bidirectional | Port A4 high-sink (HS) I/O with UART1 receive as default alternate function; the ROM bootloader pulls this pin up during activation and it returns to floating before the bootloader exits. |
| 11 | PA5/UART1_TX | bidirectional | Port A5 high-sink (HS) I/O with UART1 transmit as default alternate function. |
| 12 | PA6/UART1_CK | bidirectional | Port A6 high-sink (HS) I/O with UART1 synchronous clock as default alternate function. |
| 13 | VDDA | power_in | Analog power supply. |
| 14 | VSSA | power_in | Analog ground. |
| 15 | PB7/AIN7 | bidirectional | Port B7 I/O with ADC analog input 7. |
| 16 | PB6/AIN6 | bidirectional | Port B6 I/O with ADC analog input 6. |
| 17 | PB5/AIN5 | bidirectional | Port B5 I/O with ADC analog input 5 by default; I2C_SDA is available as a remapped alternate function via AFR6. |
| 18 | PB4/AIN4 | bidirectional | Port B4 I/O with ADC analog input 4 by default; I2C_SCL is available as a remapped alternate function via AFR6. |
| 19 | PB3/AIN3 | bidirectional | Port B3 I/O with ADC analog input 3; TIM1_ETR is available as a remapped alternate function via AFR5. |
| 20 | PB2/AIN2 | bidirectional | Port B2 I/O with ADC analog input 2; TIM1_CH3N is available as a remapped alternate function via AFR5. |
| 21 | PB1/AIN1 | bidirectional | Port B1 I/O with ADC analog input 1; TIM1_CH2N is available as a remapped alternate function via AFR5. |
| 22 | PB0/AIN0 | bidirectional | Port B0 I/O with ADC analog input 0; TIM1_CH1N is available as a remapped alternate function via AFR5. |
| 23 | PE7/AIN8 | bidirectional | Port E7 I/O with ADC analog input 8. |
| 24 | PE6/AIN9 | bidirectional | Port E6 I/O with ADC analog input 9. |
| 25 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select (SPI_NSS) as its function. |
| 26 | PC1/TIM1_CH1 | bidirectional | Port C1 high-sink (HS) I/O with Timer 1 channel 1 as its function. |
| 27 | PC2/TIM1_CH2 | bidirectional | Port C2 high-sink (HS) I/O with Timer 1 channel 2 as its function. |
| 28 | PC3/TIM1_CH3 | bidirectional | Port C3 high-sink (HS) I/O with Timer 1 channel 3 as its function. |
| 29 | PC4/TIM1_CH4 | bidirectional | Port C4 high-sink (HS) I/O with Timer 1 channel 4 as its function. |
| 30 | PC5/SPI_SCK | bidirectional | Port C5 high-sink (HS) I/O with SPI clock as its function. |
| 31 | VSSIO_2 | power_in | I/O ground supply for the second I/O group. |
| 32 | VDDIO_2 | power_in | I/O power supply for the second I/O group. |
| 33 | PC6/SPI_MOSI | bidirectional | Port C6 high-sink (HS) I/O with SPI master out / slave in as its function. |
| 34 | PC7/SPI_MISO | bidirectional | Port C7 high-sink (HS) I/O with SPI master in / slave out as its function. |
| 35 | PG0/CAN_TX | bidirectional | Port G0 I/O with beCAN transmit (CAN_TX) as its function; the beCAN interface is available on STM8S208xx devices only. |
| 36 | PG1/CAN_RX | bidirectional | Port G1 I/O with beCAN receive (CAN_RX) as its function; the beCAN interface is available on STM8S208xx devices only. |
| 37 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O with Timer 1 break input (TIM1_BKIN) as its function. |
| 38 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain (T) I/O for I2C data; the P-buffer, weak pull-up and protection diode to VDD are not implemented. |
| 39 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain (T) I/O for I2C clock; the P-buffer, weak pull-up and protection diode to VDD are not implemented. |
| 40 | PE0/CLK_CCO | bidirectional | Port E0 high-sink (HS) I/O with configurable clock output (CLK_CCO) as its function. |
| 41 | PD0/TIM3_CH2 | bidirectional | Port D0 high-sink (HS) I/O with Timer 3 channel 2 as default function; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available as remapped alternate functions. |
| 42 | PD1/SWIM | bidirectional | Port D1 high-sink (HS) I/O used as the SWIM data interface; it is in input pull-up during the reset phase and after internal reset release. |
| 43 | PD2/TIM3_CH1 | bidirectional | Port D2 high-sink (HS) I/O with Timer 3 channel 1 as default function; TIM2_CH3 is available as a remapped alternate function via AFR1. |
| 44 | PD3/TIM2_CH2 | bidirectional | Port D3 high-sink (HS) I/O with Timer 2 channel 2 as default function; ADC_ETR is available as a remapped alternate function via AFR0. |
| 45 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 high-sink (HS) I/O with Timer 2 channel 1 as default function; BEEP output is available as a remapped alternate function via AFR7. |
| 46 | PD5/UART3_TX | bidirectional | Port D5 I/O with UART3 data transmit as its function. |
| 47 | PD6/UART3_RX | bidirectional | Port D6 I/O with UART3 data receive as its function; the ROM bootloader pulls this pin up during activation and it returns to floating before the bootloader exits. |
| 48 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt (TLI) as its function. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
STM8S208C8T6TR - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8s208c8t6tr-etched.step/stm8s208c8t6tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s208c8t6tr.step/stm8s208c8t6tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
7adeaa849cf9e22f, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).