component

STM8S208C8T6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm8s208c8t6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
stm8s208c8t6 / README.md
History Download
Ray Initial commit: component/stm8s208c8t6 b2e6a62 1d ago

STM8S208C8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM8S208C8T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Active-low reset pin (I/O type in the pin table) with the NRST pull-up and electrical limits given in section 10.3.7 (Table 41).
2 PA1/OSCIN bidirectional Port A1 I/O (slow output O1) that also serves as the resonator/crystal oscillator input OSCIN.
3 PA2/OSCOUT bidirectional Port A2 I/O (slow output O1) that also serves as the resonator/crystal oscillator output OSCOUT.
4 VSSIO_1 power_in I/O ground.
5 VSS power_in Digital ground.
6 VCAP power_in 1.8 V regulator capacitor connection; the external VCAP capacitor requirements are given in section 10.3.1.
7 VDD power_in Digital power supply (2.95 V to 5.5 V operating voltage).
8 VDDIO_1 power_in I/O power supply.
9 PA3/TIM2_CH3 bidirectional Port A3 I/O (slow output O1) with Timer 2 channel 3 as default alternate function and TIM3_CH1 available after AFR1 remap.
10 PA4/UART1_RX bidirectional Port A4 high-sink I/O (HS, O3) with UART1 receive; the ROM bootloader pulls this pin up during activation and returns it to floating before a return from the bootloader.
11 PA5/UART1_TX bidirectional Port A5 high-sink I/O (HS, O3) with UART1 transmit function.
12 PA6/UART1_CK bidirectional Port A6 high-sink I/O (HS, O3) with UART1 synchronous clock function.
13 VDDA power_in Analog power supply.
14 VSSA power_in Analog ground.
15 PB7/AIN7 bidirectional Port B7 I/O (slow output O1) with ADC analog input AIN7.
16 PB6/AIN6 bidirectional Port B6 I/O (slow output O1) with ADC analog input AIN6.
17 PB5/AIN5 bidirectional Port B5 I/O (slow output O1) with ADC analog input AIN5; I2C_SDA is available after AFR6 remap.
18 PB4/AIN4 bidirectional Port B4 I/O (slow output O1) with ADC analog input AIN4; I2C_SCL is available after AFR6 remap.
19 PB3/AIN3 bidirectional Port B3 I/O (slow output O1) with ADC analog input AIN3; TIM1_ETR is available after AFR5 remap.
20 PB2/AIN2 bidirectional Port B2 I/O (slow output O1) with ADC analog input AIN2; TIM1_CH3N is available after AFR5 remap.
21 PB1/AIN1 bidirectional Port B1 I/O (slow output O1) with ADC analog input AIN1; TIM1_CH2N is available after AFR5 remap.
22 PB0/AIN0 bidirectional Port B0 I/O (slow output O1) with ADC analog input AIN0; TIM1_CH1N is available after AFR5 remap.
23 PE7/AIN8 bidirectional Port E7 I/O (slow output O1) with ADC analog input AIN8.
24 PE6/AIN9 bidirectional Port E6 I/O (slow output O1) with ADC analog input AIN9.
25 PE5/SPI_NSS bidirectional Port E5 I/O (slow output O1) with SPI master/slave select SPI_NSS.
26 PC1/TIM1_CH1 bidirectional Port C1 high-sink I/O (HS, O3) with Timer 1 channel 1.
27 PC2/TIM1_CH2 bidirectional Port C2 high-sink I/O (HS, O3) with Timer 1 channel 2.
28 PC3/TIM1_CH3 bidirectional Port C3 high-sink I/O (HS, O3) with Timer 1 channel 3.
29 PC4/TIM1_CH4 bidirectional Port C4 high-sink I/O (HS, O3) with Timer 1 channel 4.
30 PC5/SPI_SCK bidirectional Port C5 high-sink I/O (HS, O3) with SPI clock SPI_SCK.
31 VSSIO_2 power_in I/O ground.
32 VDDIO_2 power_in I/O power supply.
33 PC6/SPI_MOSI bidirectional Port C6 high-sink I/O (HS, O3) with SPI master out / slave in SPI_MOSI.
34 PC7/SPI_MISO bidirectional Port C7 high-sink I/O (HS, O3) with SPI master in / slave out SPI_MISO.
35 PG0/CAN_TX bidirectional Port G0 I/O (slow output O1) with beCAN transmit CAN_TX; beCAN is available on STM8S208xx devices only.
36 PG1/CAN_RX bidirectional Port G1 I/O (slow output O1) with beCAN receive CAN_RX; beCAN is available on STM8S208xx devices only.
37 PE3/TIM1_BKIN bidirectional Port E3 I/O (slow output O1) with Timer 1 break input TIM1_BKIN.
38 PE2/I2C_SDA bidirectional Port E2 true open-drain I/O (T: no P-buffer and no protection diode to VDD) carrying the I2C data line I2C_SDA.
39 PE1/I2C_SCL bidirectional Port E1 true open-drain I/O (T: no P-buffer and no protection diode to VDD) carrying the I2C clock line I2C_SCL.
40 PE0/CLK_CCO bidirectional Port E0 high-sink I/O (HS, O3) with configurable clock output CLK_CCO.
41 PD0/TIM3_CH2 bidirectional Port D0 high-sink I/O (HS, O3) with Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available after remap.
42 PD1/SWIM bidirectional Port D1 high-sink I/O (HS, O4) used as the SWIM data interface; it is input pull-up during the reset phase and after internal reset release.
43 PD2/TIM3_CH1 bidirectional Port D2 high-sink I/O (HS, O3) with Timer 3 channel 1; TIM2_CH3 is available after AFR1 remap.
44 PD3/TIM2_CH2 bidirectional Port D3 high-sink I/O (HS, O3) with Timer 2 channel 2; ADC_ETR is available after AFR0 remap.
45 PD4/TIM2_CH1/BEEP bidirectional Port D4 high-sink I/O (HS, O3) with Timer 2 channel 1; BEEP output is available after AFR7 remap.
46 PD5/UART3_TX bidirectional Port D5 I/O (slow output O1) with UART3 data transmit UART3_TX.
47 PD6/UART3_RX bidirectional Port D6 I/O (slow output O1) with UART3 data receive UART3_RX; the ROM bootloader pulls this pin up during activation and returns it to floating before a return from the bootloader.
48 PD7/TLI bidirectional Port D7 I/O (slow output O1) with top level interrupt input TLI.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM8S208C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8s208c8t6-etched.step / stm8s208c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s208c8t6.step / stm8s208c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (103 pp, sha256 9ab3f7b6dda7af91, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF