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STM8S208C6T6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STM8S208C6T6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM8S208C6T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (I/O); its reset-pin electrical characteristics are specified in Section 10.3.7 of the datasheet. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that doubles as the resonator/crystal oscillator input (OSCIN), with slow output speed O1 (up to 2 MHz). |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that doubles as the resonator/crystal oscillator output (OSCOUT), with slow output speed O1 (up to 2 MHz). |
| 4 | VSSIO_1 | power_in | I/O ground. |
| 5 | VSS | power_in | Digital ground. |
| 6 | VCAP | power_out | 1.8 V regulator capacitor connection; the external VCAP capacitor requirements are given in Section 10.3.1. |
| 7 | VDD | power_in | Digital power supply, 2.95 V to 5.5 V operating voltage. |
| 8 | VDDIO_1 | power_in | I/O power supply. |
| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O; default alternate function is Timer 2 channel 3, remappable to TIM3_CH1 via option bits AFR1. |
| 10 | PA4/UART1_RX | bidirectional | Port A4 I/O with high sink capability, used as UART1 receive; its default state is controlled by the ROM bootloader. |
| 11 | PA5/UART1_TX | bidirectional | Port A5 I/O with high sink capability, used as UART1 transmit. |
| 12 | PA6/UART1_CK | bidirectional | Port A6 I/O with high sink capability, used as UART1 synchronous clock. |
| 13 | VDDA | power_in | Analog power supply. |
| 14 | VSSA | power_in | Analog ground. |
| 15 | PB7/AIN7 | bidirectional | Port B7 I/O, ADC analog input 7. |
| 16 | PB6/AIN6 | bidirectional | Port B6 I/O, ADC analog input 6. |
| 17 | PB5/AIN5 | bidirectional | Port B5 I/O, ADC analog input 5; I2C_SDA is available as remapped alternate function (AFR6). |
| 18 | PB4/AIN4 | bidirectional | Port B4 I/O, ADC analog input 4; I2C_SCL is available as remapped alternate function (AFR6). |
| 19 | PB3/AIN3 | bidirectional | Port B3 I/O, ADC analog input 3; TIM1_ETR is available as remapped alternate function (AFR5). |
| 20 | PB2/AIN2 | bidirectional | Port B2 I/O, ADC analog input 2; TIM1_CH3N is available as remapped alternate function (AFR5). |
| 21 | PB1/AIN1 | bidirectional | Port B1 I/O, ADC analog input 1; TIM1_CH2N is available as remapped alternate function (AFR5). |
| 22 | PB0/AIN0 | bidirectional | Port B0 I/O, ADC analog input 0; TIM1_CH1N is available as remapped alternate function (AFR5). |
| 23 | PE7/AIN8 | bidirectional | Port E7 I/O, ADC analog input 8. |
| 24 | PE6/AIN9 | bidirectional | Port E6 I/O, ADC analog input 9. |
| 25 | PE5/SPI_NSS | bidirectional | Port E5 I/O, SPI master/slave select. |
| 26 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O with high sink capability, Timer 1 channel 1. |
| 27 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with high sink capability, Timer 1 channel 2. |
| 28 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with high sink capability, Timer 1 channel 3. |
| 29 | PC4/TIM1_CH4 | bidirectional | Port C4 I/O with high sink capability, Timer 1 channel 4. |
| 30 | PC5/SPI_SCK | bidirectional | Port C5 I/O with high sink capability, SPI clock. |
| 31 | VSSIO_2 | power_in | I/O ground. |
| 32 | VDDIO_2 | power_in | I/O power supply. |
| 33 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with high sink capability, SPI master out / slave in. |
| 34 | PC7/SPI_MISO | bidirectional | Port C7 I/O with high sink capability, SPI master in / slave out. |
| 35 | PG0/CAN_TX | bidirectional | Port G0 I/O, beCAN transmit (available on STM8S208xx devices only). |
| 36 | PG1/CAN_RX | bidirectional | Port G1 I/O, beCAN receive (available on STM8S208xx devices only). |
| 37 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O, Timer 1 break input. |
| 38 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (P-buffer and protection diode to VDD not implemented) used as I2C data. |
| 39 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (P-buffer and protection diode to VDD not implemented) used as I2C clock. |
| 40 | PE0/CLK_CCO | bidirectional | Port E0 I/O with high sink capability, configurable clock output. |
| 41 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O with high sink capability, Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are remappable alternate functions. |
| 42 | PD1/SWIM | bidirectional | Port D1 I/O with high sink capability, SWIM data interface; it is in input pull-up during the reset phase and after internal reset release. |
| 43 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O with high sink capability, Timer 3 channel 1; TIM2_CH3 is a remappable alternate function (AFR1). |
| 44 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O with high sink capability, Timer 2 channel 2; ADC_ETR is a remappable alternate function (AFR0). |
| 45 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with high sink capability, Timer 2 channel 1; BEEP output is a remappable alternate function (AFR7). |
| 46 | PD5/UART3_TX | bidirectional | Port D5 I/O, UART3 data transmit. |
| 47 | PD6/UART3_RX | bidirectional | Port D6 I/O, UART3 data receive; its default state is controlled by the ROM bootloader and it returns to floating before a return from the bootloader. |
| 48 | PD7/TLI | bidirectional | Port D7 I/O, top level interrupt (TLI). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
STM8S208C6T6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8s208c6t6-etched.step/stm8s208c6t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s208c6t6.step/stm8s208c6t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
7adeaa849cf9e22f, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM8S208C6T6
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM8S208C6T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Reset pin (I/O); its reset-pin electrical characteristics are specified in Section 10.3.7 of the datasheet. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that doubles as the resonator/crystal oscillator input (OSCIN), with slow output speed O1 (up to 2 MHz). |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that doubles as the resonator/crystal oscillator output (OSCOUT), with slow output speed O1 (up to 2 MHz). |
| 4 | VSSIO_1 | power_in | I/O ground. |
| 5 | VSS | power_in | Digital ground. |
| 6 | VCAP | power_out | 1.8 V regulator capacitor connection; the external VCAP capacitor requirements are given in Section 10.3.1. |
| 7 | VDD | power_in | Digital power supply, 2.95 V to 5.5 V operating voltage. |
| 8 | VDDIO_1 | power_in | I/O power supply. |
| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O; default alternate function is Timer 2 channel 3, remappable to TIM3_CH1 via option bits AFR1. |
| 10 | PA4/UART1_RX | bidirectional | Port A4 I/O with high sink capability, used as UART1 receive; its default state is controlled by the ROM bootloader. |
| 11 | PA5/UART1_TX | bidirectional | Port A5 I/O with high sink capability, used as UART1 transmit. |
| 12 | PA6/UART1_CK | bidirectional | Port A6 I/O with high sink capability, used as UART1 synchronous clock. |
| 13 | VDDA | power_in | Analog power supply. |
| 14 | VSSA | power_in | Analog ground. |
| 15 | PB7/AIN7 | bidirectional | Port B7 I/O, ADC analog input 7. |
| 16 | PB6/AIN6 | bidirectional | Port B6 I/O, ADC analog input 6. |
| 17 | PB5/AIN5 | bidirectional | Port B5 I/O, ADC analog input 5; I2C_SDA is available as remapped alternate function (AFR6). |
| 18 | PB4/AIN4 | bidirectional | Port B4 I/O, ADC analog input 4; I2C_SCL is available as remapped alternate function (AFR6). |
| 19 | PB3/AIN3 | bidirectional | Port B3 I/O, ADC analog input 3; TIM1_ETR is available as remapped alternate function (AFR5). |
| 20 | PB2/AIN2 | bidirectional | Port B2 I/O, ADC analog input 2; TIM1_CH3N is available as remapped alternate function (AFR5). |
| 21 | PB1/AIN1 | bidirectional | Port B1 I/O, ADC analog input 1; TIM1_CH2N is available as remapped alternate function (AFR5). |
| 22 | PB0/AIN0 | bidirectional | Port B0 I/O, ADC analog input 0; TIM1_CH1N is available as remapped alternate function (AFR5). |
| 23 | PE7/AIN8 | bidirectional | Port E7 I/O, ADC analog input 8. |
| 24 | PE6/AIN9 | bidirectional | Port E6 I/O, ADC analog input 9. |
| 25 | PE5/SPI_NSS | bidirectional | Port E5 I/O, SPI master/slave select. |
| 26 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O with high sink capability, Timer 1 channel 1. |
| 27 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with high sink capability, Timer 1 channel 2. |
| 28 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with high sink capability, Timer 1 channel 3. |
| 29 | PC4/TIM1_CH4 | bidirectional | Port C4 I/O with high sink capability, Timer 1 channel 4. |
| 30 | PC5/SPI_SCK | bidirectional | Port C5 I/O with high sink capability, SPI clock. |
| 31 | VSSIO_2 | power_in | I/O ground. |
| 32 | VDDIO_2 | power_in | I/O power supply. |
| 33 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with high sink capability, SPI master out / slave in. |
| 34 | PC7/SPI_MISO | bidirectional | Port C7 I/O with high sink capability, SPI master in / slave out. |
| 35 | PG0/CAN_TX | bidirectional | Port G0 I/O, beCAN transmit (available on STM8S208xx devices only). |
| 36 | PG1/CAN_RX | bidirectional | Port G1 I/O, beCAN receive (available on STM8S208xx devices only). |
| 37 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O, Timer 1 break input. |
| 38 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (P-buffer and protection diode to VDD not implemented) used as I2C data. |
| 39 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (P-buffer and protection diode to VDD not implemented) used as I2C clock. |
| 40 | PE0/CLK_CCO | bidirectional | Port E0 I/O with high sink capability, configurable clock output. |
| 41 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O with high sink capability, Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are remappable alternate functions. |
| 42 | PD1/SWIM | bidirectional | Port D1 I/O with high sink capability, SWIM data interface; it is in input pull-up during the reset phase and after internal reset release. |
| 43 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O with high sink capability, Timer 3 channel 1; TIM2_CH3 is a remappable alternate function (AFR1). |
| 44 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O with high sink capability, Timer 2 channel 2; ADC_ETR is a remappable alternate function (AFR0). |
| 45 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with high sink capability, Timer 2 channel 1; BEEP output is a remappable alternate function (AFR7). |
| 46 | PD5/UART3_TX | bidirectional | Port D5 I/O, UART3 data transmit. |
| 47 | PD6/UART3_RX | bidirectional | Port D6 I/O, UART3 data receive; its default state is controlled by the ROM bootloader and it returns to floating before a return from the bootloader. |
| 48 | PD7/TLI | bidirectional | Port D7 I/O, top level interrupt (TLI). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
## CAD (KiCad official)
- Symbol: `STM8S208C6T6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm8s208c6t6-etched.step` / `stm8s208c6t6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s208c6t6.step` / `stm8s208c6t6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923748187979776) (117 pp, sha256 `7adeaa849cf9e22f`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm8s208c6t6-datasheet.pdf)